Boston, MA, February 10, 2011 – The SOI Industry Consortium today announced results of an assessment and characterization of Fully-Depleted Silicon-on-Insulator (FD-SOI) technology, demonstrating that this advanced CMOS silicon technology is well suited to address the increasing low-power, high-performance requirements for mobile and consumer applications. A joint collaboration between Consortium members—ARM, GLOBALFOUNDRIES, IBM, STMicroelectronics, Soitec, and CEA-Leti—has demonstrated key benefits of planar FD-SOI technology for these applications based on an ARM processor. Planar FD-SOI technology enables substantial improvements in performance and power consumption for next-generation mobile devices, delivering high-performance applications with rich multimedia and communications functionality, reduced power consumption and improved battery life.
As SoC designs increase in complexity to deliver the enhanced features required by today’s mobile consumer, designers face the challenge of continuing to reduce the voltage while maintaining the stability of the SRAM bit-cells. Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40 percent while maintaining the stability of the SRAM.
Using an ARM Cortex™ processor as a prototyping vehicle, a team of SOI Industry Consortium members demonstrated that planar FD-SOI technology enables designers to continue to decrease the voltage to reduce the overall power, while maintaining system performance.
The inherent benefits of FD-SOI can also significantly improve system performance as you transition from generation to generation. Traditionally, low-power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20 percent to 30 percent. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80 percent gain can be achieved beyond the traditional increase. This level of improvement can enable higher-performance handheld products while significantly reducing the overall system power, which translates into a superior user experience.
FD-SOI also provides a compelling manufacturing advantage compared to other potential solutions. Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost-efficient approach to further shrinking CMOS transistors.
“Through our collaboration, Consortium members have demonstrated the advantages of FD-SOI for mobile and consumer applications,” said Horacio Mendez, Executive Director of the SOI Industry Consortium. “FD-SOI is a great option to improve the key metrics for mobile markets: power, frequency, manufacturability and most importantly cost efficiency.”
“This implementation indicates that FD-SOI technology is an attractive alternative for those designing SoCs for advanced mobile devices,” said Simon Segars, Executive Vice President and General Manager, ARM, Physical IP Division. “It also demonstrates a significant opportunity for our customers to produce leading low-power, high-performance consumer devices, while potentially lowering their system cost.”
“FD-SOI represents a tremendous technology opportunity for low-power mobile designs,” said Dr. Suresh Venkatesan, Vice President, Technology Development, GLOBALFOUNDRIES. “FD-SOI offers a number of potential benefits through simplified manufacturing integration and a compelling power and frequency proposition.”
SOI, recognized as a green semiconductor technology, has been in high-volume manufacturing for over a decade, enabling high-performance computing, gaming and communications products, with hundreds of millions of SOI chips shipped. FD-SOI also allows for full design re-usability: all established design tools and methodologies are fully implementable. SOI wafer manufacturers have affirmed that the ultra-thin SOI wafers needed for FD-SOI meet all specifications and are ready for high-volume manufacturing.
“As the Chairman of the SOI Consortium, I am extremely excited about the potential that the FD-SOI technology can bring to the industry. The testing and modeling to date would indicate that FD-SOI offers an ideal combination to achieve ultra-low-power, high-performance and cost-effective manufacturability attributes. The consortium members are all working together on the development and technology evaluations, with assistance from process R&D, IP design, manufacturing members and the substrate suppliers,” said Michael Cadigan, Chairman of the SOI Industry Consortium and General Manager, IBM Microelectronics, Systems & Technology Group.
SOI Consortium Executives will be available to discuss the results at the Mobile World Congress in Barcelona, 14-17 February 2011. Please contact Camille Darnaud-Dufour, camille.darnaud-dufour@soiconsortium.org or Horacio Mendez,hmendez@soiconsortium.org to arrange an appointment.
About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Applied Materials, ARM, BroadPak, Cadence Design Systems, CEA-Leti, FEI, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech,, Kanazawa Institute of Technology , KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit www.soiconsortium.org.
