editor's blog
Subscribe Now

Go Wide

Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.

The idea behind the wide-I/O movement is predicated on use in 3D ICs, where a memory chip will be stacked on a logic chip, with the connections being made by TSVs. Instead of requiring higher-drive I/Os that connect to chip pads and traverse PCB traces to get to a memory chip (or back from the memory chip), you stay entirely within the package. An array of TSVs mean that you can handle far more I/Os that if you have to go to package pins. And the drive requirements are reduced tremendously, reducing both the size (due to smaller transistors) and power of the resulting combination.

Of course, with more connections, you get much higher bandwidth: this is a 512-bit interface. That’s a lot more data available in one chunk than you can traditionally get.

Cadence’s controller block includes traffic shaping algorithms to increase throughput as well as features to address power, including traffic sensing (so that power can respond to traffic) and an option for dynamic voltage and frequency scaling (DVFS).

This would seem to come well ahead of the standard, which is projected (no promises!) to be available to non-members in September. But, in many such standardization cases, the technical details are approved first, and then the resulting standard goes through a higher-level board approval step that largely examines the process by which the standard was set to make sure that it was done properly. 

Clearly Cadence is betting that there will be no further technical changes. Or that, if there are, they can update the IP before any customer commits to final silicon.

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Advances in Solar Energy and Battery Technology
Sponsored by Mouser Electronics and onsemi
Passive components will play an important part in the next generation of solar and energy storage systems. In this episode of Chalk Talk, Amelia Dalton, Prasad Paruchuri from onsemi, Walter Fusto from Würth Elektronik explore trends, challenges and solutions in solar and energy storage systems. They also examine EMI considerations for energy storage systems, the benefits that battery management systems bring to these kinds of designs and how passive components can make all the difference in solar and energy storage systems.
Aug 13, 2024
54,608 views