Gordon Moore celebrated his 93rd birthday at the beginning of this year (January 3). Moore and seven co-conspirators including Robert Noyce, collectively dubbed the “Traitorous 8,” left Shockley Semiconductor Laboratory en masse and founded Fairchild Semiconductor in 1957. In 1965, as Fairchild Semiconductor’s R&D Labs Director, Gordon Moore published a very short article titled “Cramming More Components onto Integrated Circuits” in Electronics magazine, written when many silicon wafers being used to make ICs measured just one inch in diameter. That brief, 4-page article laid the foundation for “Moore’s Law.” Things have come a long, long way since then.

Along the lines of Captain Barbossa’s explanation of the Pirates’ Code in the original “Pirates of the Carribbean” movie, Moore’s Law “is more of what you’d call guidelines, than actual rules.” The repetitive doubling of transistors on one semiconductor die according to a rigid timeline extending into the far future is not some sort of physical law. You won’t find it in any introductory physics textbook. It certainly was nowhere to be found in Halliday’s and Resnick’s two-book Physics set I attempted to navigate in college, with great difficulty I might add. Instead, Moore’s Law became a ruling guideline, an inescapable and self-fulfilling prophecy, that built today’s half-trillion-dollar semiconductor industry.

Moore’s Law has driven the semiconductor industry relentlessly for almost six decades. I’ve written about Moore’s Law in EEJournal many times before. In “Moore’s Law and the Seven Devices,” I wrote:

“The Fairchild Micromatrix 4500 was the industry’s first commercially successful, mask-programmable gate array – introduced all the way back in 1967! …The Micromatrix 4500 Gate Array – it’s really the world’s first commercially successful ASIC – incorporated a whopping 32 uncommitted 4-input AND/NAND gates (the output inverter could be omitted using appropriate mask wiring) that you’d connect up using two metal mask layers.

“David Laws sent me a photograph of the Micromatrix 4500 Gate Array die… Laws estimates that the Fairchild Micromatrix 4500 Gate Array incorporated 264 components, based on his visual assessment of the… die photo.

“Today’s behemoth chips fabricated with nanometer lithography incorporate several tens of billions of transistors plus many more assorted electronic components. We’ve needed only fifty years to go from two hundred components on one semiconductor die to tens of billions. By any yardstick that you might care to use, that’s a stunning achievement, and Gordon Moore predicted all of it in 1965 with the merest whiff of data – just five data points – and a massive intuitive leap.”

But these days, the original Moore’s Law is in trouble. “No Exponential Lives Forever” was the title of Gordon Moore’s plenary speech at the ISSCC’s 50th anniversary. Halving the transistor geometries at this point on the Moore’s Law curve means splitting atoms. You can do that for nuclear physics, but not when manufacturing semiconductors. So, the industry is continuing to sneak down the scaling line using EUV (actually X-ray) lithography, but more slowly than before. In addition, it’s growing chips in two dimensions that reside outside of the original Moore’s Law: up and out.

DRAM makers pioneered 3D semiconductor structures in the 1990s, but I think NAND Flash memory manufacturers were really the first semiconductor companies to truly shift to 3D manufacturing in production. My friend Jim Handy, who self-styles himself as “The Memory Guy,” has been writing about 3D NAND Flash memory for a decade or more. In his article titled “Samsung Announces 3D NAND Production,” Handy wrote:

“Samsung has announced production of its 3D NAND technology. This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

“It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology. At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell. The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor. The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates. Both worked very well, but over time the trench makers have exited the business.”

More recently, FinFETs and now nanosheet FETs and RibbonFETs – which Intel plans to use starting with its 20A process node (“A” is for “angstrom”) – are taking the 3D route to build skyward from the silicon substrate’s top surface. The third dimension is not a growth direction Moore envisioned in his original article; the chip-making world in 1965 had only just adopted planar manufacturing technology four or five years earlier. However, there’s no denying the success of 3D technology in all manner of semiconductor manufacturing at this point. It’s being used to extend Moore’s Law by building upwards in addition to 2D scaling. Strictly speaking, as envisioned in his original 1965 article, this isn’t Moore’s Law at work, but the effect is the same: cram ever more transistors into a package.

At the same time, semiconductor vendors are turning to chiplets to effectively build chips beyond current reticle limits. (IC chips approaching the size of the exposure reticle – about 800mm2 – have long been called “reticle busters,” and not in a good way.) Chiplets have become the method of choice for extending ICs beyond reticle limits by joining separate semiconductor die together using substrate interconnections. For example, Xilinx has been using chiplet construction for its largest FPGAs for a decade, starting with the Virtex-7 2000T FPGA, which incorporated four active chiplets (or “tiles”) on a silicon interposer. However, multichip packaging has been around for decades. I was writing about it in 1988, and it wasn’t new then.

One of the most extreme examples of today’s chiplet construction techniques is Intel’s Ponte Vecchio GPU, which assembles 47 active tiles into a multi-chip package. The tiles are manufactured by multiple semiconductor vendors using five different semiconductor process nodes, and the tiles are combined in one package using 2.5D and 3D assembly techniques to produce an integrated product with more than 100 billion transistors. (See my recent EEJournal article, “Intel Welcomes You to the Angstrom Era – PS: Moore’s Law is Still Dead.”) In that article, I wrote:

“Some people have claimed that Moore foresaw multichip packaging in his article. They cite this phrase:

“’It may prove to be more economical to build large systems out of smaller functions…’

“But they seem to omit the second half of this sentence:

“’…which are separately packaged and interconnected.’

“Here, Moore was clearly discussing the use of multiple individually packaged chips on one board, a staple of board-level design since integrated circuits first appeared in the 1960s. From my perspective, Moore was clearly not predicting today’s multichip packaging with this sentence.”

Later, in the same article, I wrote:

“Multichip packaging makes sense only because different process nodes deliver different cost/performance/capabilities tradeoffs, because we’re at the reticle limits of current chip-making equipment, and because 2.5D and 3D packaging techniques are now sufficiently practical and economical to make this approach work commercially. Why shouldn’t blocks and subsystems be made from the most efficient semiconductor process node possible, assuming you have the manufacturing processes needed to assemble all of these tiles or chiplets reliably and economically? Ponte Vecchio is admittedly an engineering marvel, but it’s most definitely not a monolithic chip, and so it’s not an example of the original Moore’s Law in action.

“Except for the massively mythological underpinnings of Moore’s Law, it’s really not important to most of us how Intel crams 100 billion transistors into the Ponte Vecchio package. It’s not important to systems engineers using Ponte Vecchio GPUs in their designs. It’s not important to people using graphics software or computer games that run on Ponte Vecchio GPUs. The device’s performance, power, and price (the three fundamental ‘P’s of all engineering design) are what’s important to those of us who live outside of the package.”

So, Moore’s Law might be dead, or it might be morphing into something bigger and grander, depending on your perspective. Fortunately, the spirit of Moore’s Law and Gordon Moore himself are still very much alive.

Happy birthday, Dr. Moore!

Note: This article kicks off a month’s worth of birthday articles.