Few challenges in the world of high-technology startups are as daunting as that of putting a new FPGA company on the map. Sure, there’s the obvious hurdle of coming up with a better mousetrap – against two extremely innovative and experienced mousetrap makers who most certainly have deeper pockets than you.  And deep pockets matter. If you don’t have the resources to deal with the nine-digit-dollar entry fee for new device development at competitive process nodes, you’re better off not leaving the starting line. 

Then, there’s the matter of timing the waves. Let’s say you came up with a fancy new FPGA design, and you planned to implement it at 28nm. If you started designing at about the time 28nm technology was first available, and you executed your design project perfectly, you’d at least be on an even playing field with the big established companies. (Not that the even playing field would help that much, given that the other teams have about 50x the number of players you’re fielding.) But chances are, you didn’t execute your design project perfectly, and chances are, the semiconductor fab didn’t give you top priority compared with their long-time high-paying partners. That means you launched your 28nm a year or so later than the big guys.

You’re pretty much dead in the water. 

Unless you then re-group, plunk down another couple years of sweat and another nine-digit budget, and try to catch the next wave before it crashes you against the rocks. Sounds pretty fun, doesn’t it?

This lovely scenario doesn’t even cover the REALLY tricky parts – like getting a robust, reliable design tool chain that your customers can use to productively create designs on your new chips, or having sufficient breadth and depth in your applications support team to help those customers complete their designs successfully. It also doesn’t cover what is perhaps the trickiest part of all: getting engineers to trust their project to unproven chips, designed with unproven tools, from an unproven supplier – a supplier who, if history is any guide, has a significant chance of going out of business within the first few years.

That makes trying to start a new FPGA company seem downright crazy.

This week, Achronix announced that they’re shipping their 22nm, Intel-fabbed, FinFET-having, communications-focused, high-performance FPGAs in production volumes, and they’re rolling out a new version of their accompanying design tool suite. They have real, paying customers (at least a 2-digit number of them) who have designed their devices into real production sockets – using the company’s tools and development kits and taking advantage of the company’s applications engineer support. Interestingly, this makes Achronix (by far) the first FPGA company to be in production with FinFET FPGAs. All of you who were putting money on which of the big two vendors would win that race can refund your wagers now. Neither of them will be winning.

Congratulations, Achronix. Regardless of what happens in the future, you have now accomplished the near impossible. You have run the gauntlet, descended into the hottest flames of the tech-entrepreneurial underworld, fought your way past the burned-out corpses of so many startups that attempted this route before you, and successfully emerged on the other side – a real, chip-shipping, money-earning, customer-having, tool-supporting FPGA company. Take your right hands, high-five each other, reach around and pat yourselves on the back, then raise a toast.

Now put your bubbly down and get ready for the really hard part.

In order to get this far, Achronix has taken a very intelligent, measured, and practical approach. Oh, and about ten years. That’s how long it has been since my first editorial briefing with a tiny startup that had big ideas about setting the FPGA world on fire. Achronix had invented an asynchronous programmable logic fabric that could run many times faster than the conventional LUT-based fabrics of the time. The asynchronous fabric is on the back burner now, but the experience of bringing that innovative device to market gave the company the kind of hard-earned wisdom that has led to their surviving and shipping today.

Achronix has focused on one key market: wireline. Unlike the big, established FPGA companies who are trying to grow the market by broadening their base of applications, Achronix has gone after the golden goose exclusively, which is likely to annoy the heck out of the big guys. This “focus” goes far beyond marketing and sales. Achronix designed their FPGAs with a rich and robust selection of hard IP aimed specifically at the wireline crowd. The list of hardened functions includes a 10/40/100 Gbps Ethernet MAC, DDR3 Phy and controller up to 1866 Mbps, PCI Express gen 1,2,3 with hardened DMA, and Interlaken at 100 Gbps.

This selection of hard IP starts a self-reinforcing chain of benefits for wireline designers. First, since these parts of the design are already finished, tested, and working, one of the most challenging parts of your design is already completed with zero schedule impact and zero risk. You can focus your engineering effort on your value-added part. Second, those parts of your design will run faster with less power, and will consume less silicon area, than those same functions implemented in programmable logic. Combined, that means you get a huge chunk of your design already finished and operating at lower power – at a lower cost than you would have paid for that function on a conventional FPGA. 

Furthermore, since your FPGA design tools aren’t having to synthesize and place-and-route those portions of your design, they’re left with a smaller circuit to deal with and fewer timing-critical paths to optimize. They’ll run faster and do a better job. Then, when you start iterating on your design, there are fewer areas of your circuit that can be accidentally perturbed during iteration. Few things are as frustrating as struggling to meet timing on a critical block, finally getting it right, then having it fall apart again because you made some small unrelated change in a distant part of your circuit. And, since you don’t need LUT fabric to implement those parts of your system, you can get by with a smaller FPGA than you would otherwise need. This drops the cost and power yet again. 

Following on the “lower power” theme, the FinFET technology – courtesy of Intel – comes in and reinforces that advantage. In the market today, Achronix is competing primarily against 28nm planar FPGAs. The 22nm Tri-Gate (Intel’s name for FinFET) transistors have a significant power/performance advantage – both in static and dynamic power. Combining the process advantage with the architectural advantages from the hardened IP creates a significant benefit in power consumption – and also in cost.

The company expected its “Half the power. Half the cost.” marketing message to resonate with wireline design teams. And, while prospective customers did appreciate power and cost advantages, it turned out they appreciated the ease of design benefits from the hard IP blocks even more. Achronix doubled down on this benefit as well, providing demo and reference design for common wireline applications. For some customers, a huge chunk of their application is already done for them and working – the day they take the development kit out of the box.

The thing that kills more FPGA companies than anything else is tools. Time after time, we’ve seen very smart people come up with novel new architectures for programmable logic devices. Getting those chips designed and built is no small task, but the challenge of getting robust design tools to enable the customers to use those chips is even more substantial. This is one area where Achronix is particularly proud. During the decade the company has spent getting to volume production status, they’ve managed to forge a robust, reliable, and capable design tool flow. “We don’t have all the bells and whistles of the big companies’ tools,” explains Steve Mensor, Achronix VP of Marketing, “but our tools are solid, stable, and capable.” Achronix says the latest version of their design tools (announced today) can achieve significantly better design performance than the previous version. 

The final hurdles for an aspiring FPGA company are credibility and financial stability, and these two are related. So far, Achronix’s investors seem loyal to the cause, and they have provided the company with the resources and the patience required for the monumental task of establishing a beachhead in the high-end FPGA market. It would seem that things would only get better from here – since volume shipments of high-margin devices are what FPGA companies depend on for the kind of self-sustaining cash flow that can assure a semiconductor company long-term viability.

As for credibility, Achronix says their current customers are their best advocates. While public success stories are challenging to obtain at best, the company has a number of current customers who are willing to act as references under NDA. Having another design team tell you they’ve tried a new technology and succeeded in getting it to work for them is more powerful as a confidence builder than all the PowerPoint slides in the world. While this may seem like a trivial matter, best relegated to the domain of marketing tomfoolery – for a new supplier working to win the confidence of a new customer, it is literally the difference between survival and failure.

Of course, Achronix still has a long way to go before their market share numbers show up on the radar of the big suppliers. In fact, they have a long way to go before they’re fully and truly out of “startup” mode and generating self-sustaining, profitable flows of revenue from silicon sales. But the company has certainly cleared an obstacle that none before them have passed. For that reason alone, they should have our attention.