SANTA BARBARA, CA — June 1, 2009 — Green Hills Software, Inc., the largest independent vendor of embedded software solutions, will exhibit, present and demonstrate its newest software advances next week, June 7 – 9, 2010, at the Embedded Systems Conference in Chicago, Illinois.

Visit us in Booth #213 where our seasoned embedded software veterans will demonstrate our latest software technologies and answer any questions you may have.

Also, experts from Green Hills Software will present at the conference topics that will address today’s burning issues:

1.      Topic: Designing your System for High Reliability
When: Tuesday, June 8, 2010, 2:35pm — 3:25pm
Where: Donald E. Stephens Convention Center, room 3, Medical/Safety & Security track
Who: Greg Davis, Director of Engineering, Compilers, Green Hills Software

Synopsis: While 85% of embedded designs use C and C++, these languages are notorious for their inherent lack of safety. This presentation focuses on the tools and techniques that can be used to augment any software design paradigm. Techniques include coding conventions, automatic run-time error checking, manual compile-time and run-time assertions, static analysis, and the most common mistakes to avoid.

2.      Topic: Modern Network Security Protocols for Embedded Systems
When: Tuesday, June 8, 2010,  3:30pm — 4:20pm
Where: Donald E. Stephens Convention Center, room 5, Safety & Security/Networking & Connectivity track
Who: David Kleidermacher, Chief Technology Officer, Green Hills Software

Synopsis: Learn about the most up-to-date cryptographic algorithms, network security protocols, certification standards, and how developers can practically apply these in embedded designs. An overview of the latest and most important cryptographic algorithms, such as AES-GCM and Elliptic Curves, and network security protocols, such as TLS v1.2, DTLS, and IKE v2, will be provided. The class will demonstrate how to make practical use of these tools in embedded systems and provide loads of useful advice regarding performance, power consumption, footprint, key management, certification standards, such as FIPS 140-2 and Suite-B.

3.      Embedded Virtualization: the Ultimate Open Platform
When: Wednesday, June 9, 2010, 1:30pm — 2:20pm
Where: Donald E. Stephens Convention Center, room 3, Designing for Embedded Linux (and Android)/Open Source Software track
Who: David Kleidermacher, Chief Technology Officer, Green Hills Software

Synopsis: A new generation of hypervisor technology is rapidly making its way into a wide range of electronic products. Embedded virtualization takes open source to a new level, enabling applications from any operating system to peacefully coexist on a single hardware platform. Embedded virtualization has specialized requirements, involving footprint constraints, power efficiency, and reliability. This session will introduce and compare virtualized open source operating system implementations across the most popular multicore architectures, including ARM, Intel, and Power, and explain how hypervisors can be practically applied to enable compelling new capabilities across a wide range of industries and applications.

4.      How to Choose a Multicore Processor for Embedded Networking Devices
When: Wednesday, June 9, 2010, 11:30 am — 12:20pm
Where: Donald E. Stephens Convention Center, ESC Theater
Who: David Kleidermacher, Chief Technology Officer, Green Hills Software

Synopsis: Selecting the optimal microprocessor for a design is a skill that straddles art and science, especially with emerging technologies, such as multicore, virtualization, and a myriad of on-chip co-processors, accelerators, and peripherals. Discussion of: 1. In-depth, unbiased comparisons between the latest multicore processors across all the major architectures – ARM, Intel, MIPS, and Power – from a variety of leading chip vendors, with a focus on embedded networking applications. 2. Case studies, demonstrating how seasoned veterans have made similar decisions on actual projects.

Our Green Hills Software experts will provide in booth #213 the following demos.

Virtualization and Wi-Fi Kiosk:

Green Hills Software will showcase INTEGRITY® Secure Virtualization running on the Texas Instruments OMAP3530 processor. A Linux guest operating system and various applications will be securely hosted on the INTEGRITY RTOS alongside other real-time critical native INTEGRITY applications. Safe and secure separation between the Linux kernel and applications will be demonstrated through an attack on the Linux kernel that is isolated and contained within the virtual machine, while the native INTEGRITY application continues reliable operation. This demonstration will also include a new Wi-Fi integration via the Silex Technology SX-SDCAG 802.11a/b/g radio/baseband SDIO card and with an Atheros AR6002 ROCm Chip.

With OMAP3 targeting the medical device market, the Green Hills Platform for Medical Devices provides the important support for secure guest OS virtualization and networking options. The Platform for Medical Devices significantly reduces the cost and risk of Class II and Class III medical product approval while providing faster time-to-market for customers requiring either the premarket notification process, the U.S. Food and Drug Administration’s (FDA) 510(k), or the more stringent Premarket Approval (PMA) process.

Multicore Kiosk:

The Green Hills INTEGRITY RTOS and MULTI® integrated development environment (IDE) will be showcased on the multicore Freescale QorIQ™ P2020 processor. Multicore visibility and run control will be demonstrated through various tools in the IDE including the debugger, event analyzer, and profiling tools. The INTEGRITY RTOS will be demonstrated executing in both symmetric and asymmetric multiprocessing modes (AMP and SMP).

With Freescale’s P2020 targeting the networking industry, Green Hills Software’s expertise in multicore and virtualization provide significant benefits to this market. High availability and secure isolation between networking subsystems in the Green Hills Platform for Secure Networking is assured by INTEGRITY, the world’s first Common Criteria EAL6+ certified operating system technology. The INTEGRITY advanced security architecture prevents denial-of-service attacks, while guaranteeing optimal real-time performance for packet processing applications. INTEGRITY technology secures your networking equipment at the core of the design. The advanced security architecture and inherent security policies of the INTEGRITY RTOS support safe, separate execution of routing, switching, management and guest operating systems, while providing the ideal platform to host the networking and security functionality available in the Freescale VortiQa software products.

About Green Hills Software

Founded in 1982, Green Hills Software, Inc. is the largest independent vendor of embedded development solutions. In 2008, the Green Hills INTEGRITY-178B RTOS was the first and only operating system to be certified by the NSA to EAL6+ High Robustness, the highest level of security ever achieved for any software product. Our open architecture integrated development solutions address deeply embedded, absolute security and high-reliability applications for the military/avionics, medical, industrial, automotive, networking, consumer and other markets that demand industry-certified solutions. Green Hills Software is headquartered in Santa Barbara, CA, with European headquarters in the United Kingdom. Visit Green Hills Software at www.ghs.com.

BEDFORD, MA – June 1, 2010 – GateRocket, Inc., the leading supplier of verification and debug solutions for advanced FPGAs, today announced new versions of its popular RocketDrive® product that incorporate FPGAs from the Xilinx (NASDAQ:XLNX) Virtex®-6 family of high performance programmable devices and significantly reduce the verification and debug time associated with these leading-edge devices. The Virtex-6 FPGAs are the highest performing and most advanced FPGAs available, allowing true system-on-chip (SoC) level integration that is well-suited to the needs of a wide range of electronic products.  

GateRocket’s RocketDrive cuts verification and lab debug time in half versus traditional FPGA design approaches.  This is accomplished by integrating the FPGA into the HDL simulator to provide a “hardware in the loop” process based on GateRocket’s proprietary Device Native® methodology. This technique allows execution of the design on the target FPGA device.  By combining the actual FPGA hardware and RTL simulation models in the same verification run, this solution reduces verification and lab debugging time significantly.

“Our flagship Virtex-6 FPGA family and the GateRocket verification and debug solutions have improved the development efficiency and design bring-up time for some of our most advanced customers,” said Dave Tokic, senior director for partner ecosystems and alliances at Xilinx. “We’re pleased that Xilinx Alliance Program members like GateRocket are keeping pace with our technology advancements to deliver unique solutions that reduce design time for our customers.”

Multiple configurations optimized for different user needs

The new Virtex-6 RocketDrives use the largest LX and SX devices for advanced logic and DSP applications respectively. GateRocket also offers a cost effective mid-range device configuration targeted at users who do not require the largest FPGA device in the family.  By using devices optimized for specific needs, GateRocket can pass along the cost savings for an even greater return on investment.  Each RocketDrive configuration offers the same enhanced verification performance and debug efficiency, and maintains complete compatibility with popular EDA logic simulators from Cadence, Mentor and Synopsys.

Advanced debugging with RocketVision® for Virtex-6 devices

The GateRocket solution allows designers using Virtex-6 devices to move effortlessly between RTL and the specific FPGA being targeted, combining actual FPGA hardware and RTL simulation models together in a single verification run, without changes in the design flow or methodology. This technique, called soft patch, provides engineers with the ability to make a change to one or more RTL blocks and re-run them along with the hardware implementations of the other blocks, thereby avoiding the need to rebuild the device for each fix and  enabling multiple design-change-debug iterations in a single day. The net result is a time savings of up to 50% or more over traditional verification and debug approaches.

“As the FPGA industry continues to push the performance and capacity of its devices at every process node, the verification and debug challenges faced by designers also increase in lock-step. GateRocket is committed to providing verification and debugging solutions that allow Xilinx customers to more efficiently leverage the capabilities of the most sophisticated devices by addressing FPGA complexity and delivering a significant boost in productivity,” said Dave Orecchio, president and CEO of GateRocket.

Pricing and availability

GateRocket offers support for the Xilinx Virtex-6 FPGA family with several RocketDrive configurations supporting both the LX and SX families of devices.  Pricing starts at $25,000 with availability in July 2010. 

About GateRocket

GateRocket, Inc., located in Bedford, Mass., offers electronic engineers Device Native® verification and debug solution for advanced FPGA semiconductor devices that can cut in half the verification and lab debug time for FPGA based projects. The company’s RocketVision software debug tool and its RocketDrive hardware verification system enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time-to-market, and realize more reliable and predictable results. Learn more about GateRocket online at www.gaterocket.com and sign up for a free webinar.

THAME, United Kingdom, May 24, 2010 – Imperas today announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded™ software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.

The initial result of this flow is the release of free reference virtual platforms by Imperas based on ARM and MIPS processor cores, running the Mentor Nucleus RTOS. These reference virtual platforms are available from the Open Virtual Platforms (OVP) website, www.OVPworld.org/Nucleus. The reference virtual platforms constructed from OVP open source models make it easy for embedded systems developers to use these platforms as a starting point for building their own virtual platforms. A compiled version of the Mentor Nucleus RTOS running on the reference platforms is available for demonstration. Developers interested in using the Nucleus product will need to get a license from Mentor.

“Embedded software is the key differentiator for today’s products and we need to make it easier for people to develop embedded systems,” said Glenn Perry, general manager of Mentor Graphics Embedded Software Division. “Virtual platforms are one way to accelerate software development, and we are excited that Imperas has provided a flow that enables users to run Nucleus RTOS and EDGE on OVP reference platforms.”

A virtual platform is a set of models and a simulation engine that enables the same software binaries that would run on the hardware to be executed on a software, or virtual, platform. Because instruction-accurate models do not require the full implementation details of the hardware, they can be more easily and quickly developed, enabling software development to start months before any hardware is available. In addition, software development on virtual platforms offers the benefit of simulation of any system: full visibility and controllability, unlike the limited access that hardware provides as a software development environment. Further benefits of virtual platforms include real-time simulation speed of hundreds of millions of instructions per second, and deterministic behavior, enabling simulation runs to be repeated.

“Just as we cannot imagine developing hardware without using simulation, software simulation, or virtual platforms, are moving into the mainstream of embedded software development for SoCs (systems on chips),” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Making it easier to get started with virtual platforms by releasing reference platforms with the most popular operating systems such as Nucleus RTOS provides great value to the OVP and embedded systems communities.”

About Imperas (www.Imperas.com)

For more information about Imperas, please go to the Imperas website.

About the Open Virtual Platforms Initiative (www.OVPworld.org)

For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.

Mentor Graphics and Nucleus are registered trademarks and Mentor Embedded is a trademark of Mentor Graphics Corporation. MIPS, Malta and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. Imperas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.