feature article
Subscribe Now

WHITE PAPER – Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints

altera.jpg

Introduction

Altera first introduced the 180-nm CMOS-technology HardCopy® series of ASICs, with their “seamless prototyping” capabilities, in 2001. The premise behind this first-generation HardCopy ASIC product was to “harden” the look-up table (LUT) structure of the FPGA and replace the programmable switch fabric with a direct wire (ASIC) interconnect using a small number of customized interconnect layers. Other blocks of “hardened” logic in the FPGA prototype, including I/Os, phase-locked loops (PLLs), memories, and serializer/deserializer (SERDES) channels, are used verbatim in the HardCopy ASIC. Since the introduction of that first-generation device, Altera has offered subsequent HardCopy ASIC products in 130-nm, 90-nm, and 40-nm CMOS technology. The HardCopy ASIC has attributes similar to gate array technology in that common partially fabricated “bases” are staged in inventory. The tape-out of a specific design results in a two-metal/two-via set of masks of custom metallization layers that define aunique device. The base wafer is then processed with custom metal masks, and tested and assembled in a package that is 100 percent socket-compatible and based on the same silicon process as the FPGA prototype.

This new HardCopy ASIC results in lower NRE costs versus comparable standard-cell implementations, and reduces the time to fabricate the ASIC since base wafers are pre-staged up to the custom interconnect wafer processing steps. The HardCopy ASIC is feature-equivalent to the corresponding Altera® Stratix® series FPGA, and offers comparable resources as the FPGA but with reduced die size and power. The final HardCopy ASIC is a pin-for-pin replacement of the FPGA prototype; therefore, the same system board and software can be retained between prototyping/field  trials and the final production device. Additional overall board savings can be realized by using the HardCopy ASIC for production, since it requires no boot device. The flash memory boot device does not need to be mounted on the HardCopy version of the board.

Author: Larry Landis, Senior HardCopy Project Manager, HardCopy Product Group, Altera Corporation


Leave a Reply

featured blogs
May 21, 2025
The term "brassed off"'”an informal British idiom meaning annoyed, fed up, or unhappy'”reflects a kind of period-specific British vernacular that has faded in modern times...

featured paper

How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability

Sponsored by Siemens Digital Industries Software

Through real-world examples from Intel and Google, we highlight how Calibre’s DesignEnhancer maximizes layout modifications while ensuring DRC compliance.

Click here for more information

featured chalk talk

Solutions for General Precision Location Tracking
In this episode of Chalk Talk, Arnaud Le Lannic from u-blox, Greg Makar from the YAGEO Group and Amelia Dalton explore the benefits of GNSS for general precision location tracking. They investigate the biggest challenges associated with these kinds of designs, the solutions best suited for vehicular asset tracking and the mounting options available for these solutions.
Apr 21, 2025
34,561 views