The low-cost FPGA battle is now officially on fire. Not that long ago, the FPGA race was two-dimensional – whoever could provide the most programmable logic running at the highest Fmax was the winner. Considerations like cost, power, and feature sets were almost irrelevant. The people (telecom infrastructure) buying FPGAs were scrambling to deploy as much bandwidth as they could as quickly as possible. They had big budgets and bigger power supplies. The FPGA business was relatively simple.
As the technology has matured and broadened, however, specialization has taken over. It may seem paradoxical that a technology touted for its general-purpose applicability and extreme flexibility would begin to be differentiated by specialization, but that is exactly what is happening. The number of dimensions to the “best FPGA for my job” decision has exploded, and designers around the world are faced with a complex matrix of factors to consider in choosing the best FPGA for their application.
The specialization started not that long ago (in market time) when FPGA companies got the idea to create “low-cost” or “value-based” FPGA families. They reasoned that their large devices had grown so much and so quickly that they might be leaving behind a robust market for their smaller devices. They also noticed that the same technology advances that made their biggest and fastest devices so big and fast could also be applied to make more modest devices very, very inexpensive. Any way you want to do a comparison, today’s low-cost FPGAs are orders of magnitude cheaper per capability than anything available even at the beginning of this decade.
This week, Xilinx rolled out a new 90nm low-cost FPGA family and reinforced a trend toward even greater specialization and cost-optimization. Xilinx’s new Spartan-3A is optimized for cost-per-I/O instead of cost-per-logic. Until this year, low-cost FPGA families could be rated on something like a cost-per-gate scale. You paid for a certain number of LUTs, and you got a proportional amount of other resources (I/O, multipliers, memory) thrown in. For many designs, however, the logic content was not the gating factor. Design teams often found themselves buying larger devices, not because they needed more core resources, but because their design required more I/O.
Xilinx has attacked that market with Spartan-3A.
Spartan-3A is a continuation of this optimization trend, which actually started with Spartan-3E last year. The original Spartan-3 line had a mainstream balance of I/O and logic. However, Xilinx wanted to provide a cheaper device for designs that didn’t need as much I/O as they were providing. They essentially dropped one of the two I/O rings of Spartan-3, creating the smaller die size (and lower cost) of Spartan-3E. Now, they have designed Spartan-3A in the opposite direction, with less logic and more I/O.
Confused yet?
Let’s break it down:
Spartan-3 – highest density, balance of I/O and logic – From 1728 to 74,880 logic cells, 4 to 104 multipliers, 72K to 1872K of block RAM, and 63 to 784 user I/O.
Spartan-3E – lower density, higher ratio of logic to I/O – From 2160 to 33,192 logic cells, 4 to 36 embedded multipliers, 72K to 648K of block RAM, and 66 to 376 user I/O.
Spartan-3A (the new one) – lower density, higher ratio of I/O to logic – From 1584 to 25,344 logic cells, 3 to 32 multipliers, 54K to 576K of block RAM, and 108 to 502 user I/O.
Image courtesy Xilinx
Spartan-3A has a few additional goodies thrown in as well.
First off, they learned some important lessons from the less-than-rockstar Spartan-3L line (which augmented the original Spartan-3 devices with additional power modes for low-duty-cycle power-sensitive applications). Spartan-3A includes “suspend” and “hibernate” modes – somewhat analogous to the modes of the same name in Windows-based laptops. Suspend mode reduces static power by over 40% while keeping the device active for a fast wake-up cycle. “Hibernate” mode actually allows the device to be basically powered-down completely with the penalty of a longer reconfiguration and wake-up cycle.
Second, they added a serialization scheme dubbed “Device DNA” which encodes a unique serial number into each device that can be used for authentication within the design. The serialization capability primarily targets both overbuilding and subscription-based services in FPGA-enabled systems.
Third, since this is the I/O-rich version of the Spartan-3 family, they threw in a user-controllable dynamic delay to center the data-to-clock time, allowing lower-cost memories to be used. They also beefed up support for I/O standards with a too-long-to-publish list of supported standards, notably including PCIe (not the PHY layer), USB, CAN, and SPI. It also supports DMDS and PPDS differential standards with on-chip differential termination. In the RAM department, Spartan-3A also has both DDR and DDR2 memory interfaces.
Spartan-3A also has a new version of the multi-boot capability for designs that will be updated in the field. The new system allows “n” configurations to be stored in system flash, and the device can be set up to boot from the latest good configuration, maintaining the integrity of the original “golden” configuration even without a proven-successful upload of a replacement version.
This kind of specialization has already led to multiple FPGA vendors offering devices with prices as low as single-digit dollars for smaller densities. In many markets, those pennies of cost difference add up to the deciding factor in winning a socket in a tightly-packed high-volume BOM. Since these are highly coveted sockets for FPGA companies, there are already a host of offerings – with more new ones appearing seemingly every month.
How much competition is there? Let’s run through the some of the current roster. Just in 90nm SRAM devices, in addition to the Xilinx offerings above, Altera’s Cyclone II line has a similar density range to Xilinx’s Spartan-3 with slightly different mixes of multipliers, memory, and I/O. Lattice Semiconductor’s ECP2 family also weighs in with similar densities, performance, and features, but with a beefed-up DSP block. Lattice’s ECP2-M family adds SerDes I/O to the low-cost mix. Outside the 90nm SRAM domain, Lattice’s XP family also brings on-chip non-volatile reconfiguration memory to the party. Actel comes at the low-cost market from a completely different direction, offering non-volatile flash-based devices that excel in areas such as total BOM cost and power consumption. QuickLogic targets more focused application areas with non-volatile antifuse-type devices that are crafted to meet the requirements of specific design problems such as low-power HDD control in media players.
Xilinx targets all the Spartan-3 families at the higher-volume sockets that tend to be closer to the end-user edge of the voice/video/data network trio. Specifically, applications like flat-panel displays and set-top boxes are in their sights. Xilinx says that these markets, which include consumer, industrial, and others have accounted for the majority of the company’s growth over the past five years. It is also obvious that these markets represent a huge chunk of the incremental market pie that all FPGA companies are now racing to slice.
Don’t expect this simple I/O vs core segmentation to be the end of the specialized low-cost FPGA game. If we take Xilinx’s Virtex family as an example, we already see devices separated by I/O, density, DSP resources such as multipliers, memory, and additional features such as embedded hard processors. You don’t have to blur your eyes too much to see similar things happening with Spartan-class devices.
The new Spartan-3A family has two devices (XC3S700A, and XC3S1400A), both shipping today, with all devices expected by Q2’07. Xilinx has also announced a starter kit available now for $199.
