editor's blog
Subscribe Now

Emulation: 3B Gates, 3 MHz

In the first major emulator news since Synopsys gobbled up EVE, Synopsys announced the next generation of the EVE platform, ZeBu 3. And, as with pretty much any emulator story, the top line has to do with capacity and performance: how much design can I cram in there and how fast will it go?

They claim industry-leading 3 MHz (with one example going as high as 3.5 MHz), as compared to what they say is a competition range more around 1-1.5 MHz (I’ll let the comps comment on whether or not that’s a representative number). As to capacity, you can stitch up to 10 of their boxes together for a total of 3 billion gates.

They also mention a number of different use modes for emulation, which are morphing as capabilities both inside and outside the emulator evolve. One in particular caught my eye because of how it contrasts with past usage.

Once upon a time, a significant use model for an emulator was to accelerate simulation. If there was a piece of the hardware that was taking too long to simulate – and in particular if it didn’t need simulator-level observability (remember: in a simulator, you can theoretically access every node; in actual hardware, you can only access those nodes that have been provisioned for access) – then you could implement that function in hardware and have the simulator call it as needed.

That ended up shining the spotlight on a significant bottleneck: handing off the function to the emulator, which required specifying pin-level signals across the interface. This led to the development of the transaction-based SCE-MI 2 interface, which abstracted away the detailed pin-level interface, making it all go so much faster.

That’s all old news. As emulator capacity and speed have improved, the focus has moved more to acceleration of software execution in SoCs. Not only does the emulator execute the software more quickly than a simulator can, features like save and restore can allow you to capture the state, say, after boot-up, and start there rather than having to go through the entire boot sequence every time. Yes ,you could theoretically do this with simulation as well, but simulating software just takes too long.

So we’ve gone from mostly verifying by simulation (on a PC) to doing much more of the verification on an emulator, now that it’s big enough. But you know… we’re never satisfied, are we? Give us an inch, and we want another inch. Yes, we can run software fast, but we don’t care about all of the software, or perhaps we don’t care about all of it in as much debug detail. Believe it or not, this software is taking too long to run on the emulator.

So what to do? How about running it on a virtual platform? Virtual platforms abstract away the low-level execution details, and so they can run much faster. So now, in a complete role reversal, the emulator can offload software execution to a PC running a virtual platform, which acts as an accelerator for the emulator – the very same emulator (or a bigger, faster version) that used to be an accelerator for the PC doing simulation. Synopsys refers to this as “hybrid mode,” one of the various use modes that ZeBu 3 supports.

What goes around…

You can get more details on all of those modes as well as the other speeds and feeds in their release.

Leave a Reply

featured blogs
Jul 11, 2025
Can you help me track down the source of the poem titled 'The African Tigger is Fading Away'?...

Libby's Lab

Libby's Lab - Scopes out Littelfuse C&K Aerospace AeroSplice Connectors

Sponsored by Mouser Electronics and Littelfuse

Join Libby and Demo in this episode of “Libby’s Lab” as they explore the Littelfuse C&K Aerospace Aerosplice Connectors, available at Mouser.com! These connectors are ideal for high-reliability easy-to-use wire-to-wire connections in aerospace applications. Keep your circuits charged and your ideas sparking!

Click here for more information

featured paper

Maximize Power Efficiency in Embedded Applications with Agilex™ 5 E-Series FPGAs and SoCs Memory Solutions

Sponsored by Altera

Learn how Altera Agilex™ 5 FPGAs and SoCs deliver up to 1.9× lower system power than Zynq UltraScale+ without sacrificing performance. This white paper dives into real benchmark data, memory interface efficiency, and architectural advantages that make Agilex 5 the smart choice for embedded, vision, and AI edge applications. Optimize for power, performance, and design simplicity.

Click to read more

featured chalk talk

Simplifying Position Control with Advanced Stepper Motor Driver
In this episode of Chalk Talk, Jiri Keprda from STMicroelectronics and Amelia Dalton explore the benefits of the powerSTEP01 is a system-in-package from STMicroelectronics. They also examine how this solution can streamline overall position control architecture, the high level commands included in this solution and the variety of advanced diagnostics included in the powerSTEP01 system-in-package.
Jan 21, 2025
30,952 views