May 2012 – EEJournal

Pulsic Adds Guided Flows

May 31, 2012

Pulsic has been gradually taking their technologies and turning them into flows. We saw that last year with their planning tools; now place and route are getting the treatment.

They’ve announced a placer and a router for custom digital design and a router for custom analog design. Note that they don’t have one bucket for “custom” that handles both digital and analog since the two typically involve different problems that need solving.

They’ve incorporated automation … Read More → "Pulsic Adds Guided Flows"

Optimizing Power at the Architecture Level

by Jim Turley

May 30, 2012

When Mentor handed their flagship HLS product, Catapult C, to Calypto almost a year ago, there were a lot of questions about the move. There could be technical, financial, personnel, all kinds of reasons.

Well, at least from a technical standpoint, Calypto just announced what they say was the driving factor: the natural synergy between Catapult C and the Calypto tools. In particular, their PowerPro tool, used for optimizing power.

Automated power optimization typically happens at a low level – typically using netlists ( … Read More → "Optimizing Power at the Architecture Level"

Small single-package IMU

by Kevin Morris

May 29, 2012

Bosch-Sensortec recently announced a new integrated IMU, the BMI055.

Which, amongst other things, brings up the question: exactly what is an IMU? While researching this for a gyroscope article couple of years ago, I found that the term (which stands for “inertial measurement unit”) was used to refer generically to a class of sensors that use some type of inertia as a way of sensing motion. That inertia might be linear (using an accelerometer) or rotational (using a gyroscope).

2 Spicey?

by Amelia Dalton

May 25, 2012

Tanner just announced the integration of Berkeley Design Automation’s (BDA’s) FastSPICE into their flow. You may remember Tanner as a company that does things their own way, offering a full suite of tools for custom design. Including their own T-SPICE.

And their own T-SPICE doesn’t seem to be going away; it’s not being replaced by FastSPICE. I got a chance to talk about that with Vice President of Marketing and Business Strategy John Zuk to … Read More → "2 Spicey?"

Cadence Supports NVMe

by Dick Selwood

May 16, 2012

Last year, a new standard was overlaid on PCI Express (PCIe) to reset the way non-volatile memory (NVM) is accessed. To date, solid-state disk (SSD) access methodologies had been modeled around the existing mechanisms and limitations surrounding “spinning media” – hard drives. As solid-state memories start to proliferate in roles that used to be dominated by hard drives, those limitations and mechanisms change.

The new standard that accomplishes this is called NVM Express (NVMe), and it uses the basics of PCIe to handle moving the data around, since that’s often how these memory … Read More → "Cadence Supports NVMe"

Graphene Quilts

by Amelia Dalton

May 10, 2012

A while back we looked at wide bandgap materials like GaN when used for power devices, but, along with power comes heat and the need for it to be dissipated. GaN isn’t great for that; the old sapphire substrates were very bad, and newer (and more expensive) SiC substrates are better but not sufficient, according to researchers at UC Riverside.

Metal is often used as a heat sink, but its ability to do so in very thin films dissipates because the main & … Read More → "Graphene Quilts"

Powering Up Power Analysis

by Kevin Morris

May 8, 2012

Apache has just released their latest RedHawk version, RedHawk-3DX. In it they’ve focused on areas of growing importance for power: 3D ICs, working at the RTL level, and scaling up the size of sub-20-nm designs.

Power is of particular concern for 3D ICs because of the fact that a “cube” of silicon is much harder to cool than a plane. And it’s not a monolithic cube; it’s a bunch of interconnected planes that can become detached if you’re not careful. Even the TSVs can be … Read More → "Powering Up Power Analysis"

FPGA Prototype Debug Access

by Jim Turley

May 7, 2012

When tracing events on any kind of system, it’s always faster to go local: the farther away the data has to go, the slower it goes. Which is why FPGAs are nice in that their internal memory can be used as a trace buffer, allowing really fast capture.

But that also means that you have to have that memory available. Synopsys has announced a daughter card for their HAPS prototype systems that allows fast capture to an off-chip memory. It uses their custom HAPS-TRAK connector. The clock can run over 200 MHz, but it’s … Read More → "FPGA Prototype Debug Access"

The New (Pro)Vocative

by Bryon Moyer

May 7, 2012

OK, going off script here a bit…

English has been much simplified over the years as compared to its long-ago forebears. Yeah, it’s complicated in its irregularity, but structurally, we’ve lost, among other things, the many cases that other languages use to decline their nouns. Those of you that learned German know of the nominative, accusative, dative, and genitive. But there are many other cases in different languages.

One of them is the vocative case. This is used when addressing someone directly. Given two sentences, “Bob will go to … Read More → "The New (Pro)Vocative"

High-Sigma Simulations

by Amelia Dalton

May 4, 2012

We’ve noted before that the meaning of “corners” is much less obvious for analog circuits than it is for digital. Solido noted in a recent announcement that memory design in particular highlights the challenge. Memories are built of analog circuits that are repeated numerous times, and getting them all to yield on aggressive processes with enormous variation is a tough job.

They say that the standard Monte Carlo “run enough samples to cover the space, and then interpolate … Read More → "High-Sigma Simulations"