Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.
The idea behind the wide-I/O movement is predicated on use in 3D ICs, where a memory chip will be stacked on a logic chip, with the connections being made by TSVs. Instead of requiring higher-drive I/Os that connect to chip pads and traverse PCB traces to get to a memory chip (or back from the memory chip), you stay entirely within the package. An array of TSVs mean that you can handle far more I/Os that if you have to go to package pins. And the drive requirements are reduced tremendously, reducing both the size (due to smaller transistors) and power of the resulting combination.
Of course, with more connections, you get much higher bandwidth: this is a 512-bit interface. That’s a lot more data available in one chunk than you can traditionally get.
Cadence’s controller block includes traffic shaping algorithms to increase throughput as well as features to address power, including traffic sensing (so that power can respond to traffic) and an option for dynamic voltage and frequency scaling (DVFS).
This would seem to come well ahead of the standard, which is projected (no promises!) to be available to non-members in September. But, in many such standardization cases, the technical details are approved first, and then the resulting standard goes through a higher-level board approval step that largely examines the process by which the standard was set to make sure that it was done properly.
Clearly Cadence is betting that there will be no further technical changes. Or that, if there are, they can update the IP before any customer commits to final silicon.
