SANTA CLARA, CA – September 29, 2014 – ATopTech, a leader in next generation physical design solutions, continued their ongoing collaboration with TSMC by further optimizing ATopTech physical implementation tools to support advanced designs in TSMC 16nm FinFET Plus (16FF+) V0.9 Design Rule Manual and SPICE model. Aprisa™ and ApogeeTM, ATopTech’s place and route solutions, have completed design rule support plus four additional individual tool certification projects to enhance quality of results, including design correctness, routability, timing, power, area and manufacturability for designs in 16FF+. The certification is on-track to be extended to V1.0 and will be concluded by November 2014.
In April, ATopTech announced that Aprisa and Apogee had passed TSMC’s APR tool certification in 16nm FinFET V1.0, where all 16FF design rules and methodologies were validated within the ARM Cortex™ A15 quad-core processor design hardening flow. Now, when customers download the Aprisa/Apogee Technology File for 16FF+ directly from TSMC, allowing them to begin 16FF+ designs immediately, the solution will include complete design rule support plus methodologies for design PPA improvement:
- Design enablement for 16FF+ DRM
- CPODE design solution
- Low-vdd timing optimization
- Waveform propagation effect on delay calculation
- Hold uncertainty constraints support
“Our continuing collaboration with TSMC and mutual customers allows us to deliver the advanced physical implementation solutions that our customers expect from ATopTech,” said Jue-Hsien Chern, CEO of ATopTech. “As always, we are focused on delivering faster total turn-around time and best quality of results for physical design projects.”
“The collaboration between ATopTech and TSMC ensures that joint customers realize the full potential of FinFET technology at 16nm,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “We will continue to work with ATopTech to drive innovation for physical design.”
About Aprisa
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines,” such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
About Apogee
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floorplanning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
