Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx’s Vivado tool suite.

Click the link below to download a free guidebook entitled “UltraFast Design Methodology Guide for the Vivado Design Suite.”

Click the link below to watch a video entitled “Using the Vivado Timing Constraint Wizard.”