Cadence is expanding its collaboration with Intel Foundry by officially joining the Intel Foundry Accelerator Design Services Alliance ! This collaboration amplifies both companies' efforts to drive innovation, support advanced chip design, and solidify Intel Foundry as ...

Next-generation suite includes AI-driven equivalence, ECO automation, and low-power static signoff products To address the impact of growing SoC design complexity on formal equivalence checking, Cadence has launched Conformal AI Studio—a new suite of logic equivalence check...

If you're a chip designer or verification engineer, you have likely spent countless hours stressing over whether your design block is functionally accurate; in other words, "Will my chip actually do what it's supposed to?" Today, Cadence is announcing the ...

Virtuoso Studio IC23.1 ISR13 production release is now available at Cadence Downloads . The README.txt file in the installation directory provides information about supported platforms and other release compatibility. IC23.1 ISR13 Here are the highlights from the recent Virtu...

The data center industry is on the brink of rapid transformation, driven by emerging technologies that promise to reshape its future. To assess the current ability of the data center industry to capitalize on the technologies that could transform it, Cadence's latest rep...

Designs are tested in the labs for various electrical compliance tests defined in the electrical compliance test specifications before getting certified. There are defined processes and steps that a design must go through for such testing. Such tests are focused tests and nee...

The Cadence MSA team had a GREAT DesignCon highlighting how Cadence can help you accelerate your PCB and advanced IC packaging design cycles with electromagnetic, electronic, and thermal system analysis, and tackle advanced IC packaging and cross-platform challenges. Here’s...

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get larger, the time it takes for the whole model to be loaded in Cadence Perspec Composer might become meaningful. In this blog, we will look into two practices that help you reduce this time. Sa...

The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.

With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.

New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Learn how Switch, a leading designer, builder, and operator of U.S. exascale data centers, is taking their data center’s cooling capabilities even further. In the past 20 years, Switch has built some of the densest air-cooled data center environments. With AI taking off in the last couple of years, see how they were able to deploy many of the first NVIDIA H100 clusters inside using Cadence’s Reality Digital Twin Platform for pre-modeling, design, and validation.facilities.

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

In the AI era, as the signal-data rate increases, the signal integrity challenges in server designs also increase. Wiwynn provides hyperscale data centers with innovative cloud IT infrastructure, bringing the best total cost of ownership (TCO), energy, and energy-itemized IT solutions from the cloud to the edge.