industry news
Subscribe Now

Xenergic’s SRAM for next generation of ultra-low power products

Xenergic was selected by Bosch Sensortec to provide ultra-low power SRAM for their sensing  solutions based on microelectromechanical systems (MEMS). Bosch Sensortec GmbH, a fully owned  subsidiary of Robert Bosch GmbH, develops and markets a wide portfolio of microelectromechanical  systems (MEMS) sensors and solutions tailored for smartphones, tablets, wearables and hearables,  AR/VR devices, drones, robots, smart home and IoT (Internet of Things) applications. 

Xenergic’s memory solution will enable Bosch Sensortec to add more features and significantly  extend the battery lifetime in their products. Richer set of functionalities such as integrated AI/ML  features are demanded in next generation of sensor market. However, power is a limiting factor for  realization of these functionalities.  

On-chip memories are among the largest blocks in digital integrated circuits. On average, the area  share is around 70% and their power share is often more than 50%. This is a major hurdle for  implementing richer functionalities and extending the battery lifetime in low-power MEMS and  system on chips (SoC).  

Xenergic provides ultra-low power SRAM IP with its MemoryTailorTM. The MemoryTailorTM, provides  Bosch Sensortec with a unique memory solution, optimized for each circuit’s specific design  requirements such as voltage, speed and area constraints.  

“Working with Bosch Sensortec and their very skilled team in low power design is a privilege and  great experience. Combined, our technologies redefine the power boundaries in sensor design” says  Babak Mohammadi, CEO of Xenergic. 

Xenergic AB, based in Lund, Sweden, is offering on-chip memory (SRAM) solutions with a  revolutionizing low power consumption for digital integrated circuits such as AI/ML applications,  MEMS products, image sensors, low power Bluetooth, IoT modems and edge processors. The  product portfolio consists of single and dual rail SRAM with single port, two port and dual port  configurations. It is currently implemented in most major used process technologies and typically  reduces the power consumption of an entire SoC by 70-90%. 

Leave a Reply

featured blogs
May 2, 2025
I can safely say that I've never seen a wheeled-legged robot that can handle rugged terrains, muddy wetlands, and debris-strewn ruins like this...

featured paper

How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability

Sponsored by Siemens Digital Industries Software

Through real-world examples from Intel and Google, we highlight how Calibre’s DesignEnhancer maximizes layout modifications while ensuring DRC compliance.

Click here for more information

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
74,669 views