industry news
Subscribe Now

Primarius NanoSpice™ Simulator Certified for Samsung Foundry 3nm/4nm Process Technology

  • Enables Samsung Foundry customers achieve precision accuracy
  • Provides stable convergence for analog IP, large capacitance with large netlists

SAN JOSE, CALIF. –– June 26, 2024 –– Primarius Technologies today announced that its NanoSpice™ universal parallel SPICE simulator has been validated and certified for Samsung Foundry’s 3/4nm technology. NanoSpice™ helps Samsung Foundry’s customers to achieve precision accuracy.

Samsung’s 3/4nm process technology is engineered to improve overall yield, reduce power consumption and improve performance over previous process nodes, which requires fast and accurate circuit simulation and verification tools to support advanced IC designs. Verified under Samsung Foundry’s EDA certification program in this process technology, NanoSpice™ provides stable convergence for analog IPs, large capacitance with large netlist including post-layout information which help Samsung Foundry’s customers to design with full confidence, shortening design cycle while achieving the highest accuracy.

As a breaking generation high-capacity, high-performance parallel SPICE simulator, NanoSpice™ is designed for the most challenging simulation jobs, such as large post-layout analog circuit simulations that require high capacity, speed and accuracy all at the same time. Its superior parallelization technologies enable efficient circuit simulation up to 50 million circuit elements.

“Samsung and Primarius together have achieved success with NanoSpice™ certification at Samsung Foundry’s 3/4nm process. This collaborative partnership allows both companies to deliver the competency required to verify advanced and innovative IC designs to help drive the rapidly growing IC markets and applications,” said Sangyun Kim, Vice President and head of Foundry Design Technology Team at Samsung Electronics. 

“Samsung has been a long-term customer of our EDA products and solutions, and we continue to advance our technology to cope with the simulation challenges ahead with cutting edge technologies.” remarked by Dr. Lianfeng Yang, President of Primarius. “We embrace the opportunity to be the part of the ecosystem supporting these critical process nodes, NanoSpice™ build with performance and accuracy to solve the toughest design verification problems with its full range of simulation capacities from small blocks to full chip designs and can help achieve goals that would be difficult to reach without our circuit simulation solutions.”

About Primarius

Primarius Technologies (688206.SH) is a global electronic design automation (EDA) company providing innovative Design Technology Co-Optimization (DTCO)-enabled EDA solutions for advanced technology development, and complex full custom designs including analog, mixed-signal and memory circuits. Primarius provides the industry’s de facto golden SPICE modeling solution adopted by most of the leading semiconductor companies for more than a decade, and leading SPICE/FastSPICE technologies proven by leading memory and SoC design companies worldwide. Its design enablement EDA solutions enable a full coverage of fab technology development and fabless COT flow development including device testing systems, SPICE modeling and PDK development solutions, and standard cell library characterization solutions. Built around an innovative SPICE/FastSPICE dual engine, Primarius provides a complete circuit simulation and analysis solution with comprehensive high-sigma yield and signal integrity analysis, aging and EM/IR, ESD simulation and advanced circuit checking capabilities. Primarius also provides a complete full custom design environment with advanced circuit design and optimization, layout automation and physical verification functions, and hierarchy design planning and timing analysis solutions for advanced SoC designs. Visit Primarius Technologies for more information.

Leave a Reply

featured blogs
May 16, 2025
Whatever the age into which you were born, if you were a kid enjoying something, the odds were that it was corrupting your soul....

featured paper

How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability

Sponsored by Siemens Digital Industries Software

Through real-world examples from Intel and Google, we highlight how Calibre’s DesignEnhancer maximizes layout modifications while ensuring DRC compliance.

Click here for more information

featured chalk talk

Voltage Translators: An Architecture for Every Application
Sponsored by Mouser Electronics and onsemi
In this episode of Chalk Talk, Bob Card from onsemi and Amelia Dalton explore the multitude of benefits of voltage translators. They investigate the challenges associated with I/O voltage disagreement, the voltage translator architecture for every IC-to-IC protocol and how you can take advantage of onsemi’s Treo Analog and Mixed Signal Platform for your next design.
Apr 21, 2025
31,784 views