Delivers predictable high compression with only one pair of test data pins

MOUNTAIN VIEW, Calif., November 2, 2009 — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced a new capability in DFTMAX(tm) compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. As designers … Read More → "Synopsys extends DFTMAX compression to reduce the cost of pin-limited test"

Topics include System-Level Design, VMM Verification Methodology and a multi-tool IPL Flow Demonstration

MOUNTAIN VIEW, Calif., Nov. 2 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of “Groovy Green Computing: Battling the Mushrooming Use of Power.”
WHO: The event is recommended for EDA tool developers, IC design engineers, and IP providers to discuss the industry-critical topics … Read More → "Synopsys EDA Interoperability Forum to Feature Subodh Bapat Keynote on Green Computing"

International Test Conference
AUSTIN, Texas–(BUSINESS WIRE)–Mentor Graphics Corporation (NASDAQ: MENT) today outlined its strategy and roadmap to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, low-power, mixed-signal systems-on-chip (SOCs). As part of this strategy, Mentor is uniting its award-winning embedded compression and automatic test pattern generation (ATPG) technology with the leading built-in self-test (BIST) technology from recently acquired LogicVision into a new product line, called Tessent™. The Tessent line is the industry’s most comprehensive set of design-for-test and silicon test solutions, and … Read More → "Mentor Graphics Outlines Strategy to Unify Silicon Test and Yield Analysis"

MOUNTAIN VIEW, Calif., Oct. 30 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Juniper Networks has signed a multi-year business agreement establishing Synopsys as its primary EDA partner. Under the new agreement, Juniper will use Synopsys’ Galaxy(TM) Implementation and Discovery(TM) Verification Platforms to meet their expanding chip development needs.

“Synopsys has played a key role in helping us execute on our broad open foundry strategy, including the successful migration of some of our leading designs to advanced process nodes,” said R.K. … Read More → "Juniper Chooses Synopsys as Its Primary EDA Partner"

Connectivity IP leader continues to innovate with the DesignWare USB 2.0 picoPHY – the first PHY IP to support USB 2.0 Battery Charging v1.1 and OTG 2.0 specifications

MOUNTAIN VIEW, Calif. – October 29, 2009 — Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of the new DesignWare(R) USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in more than 50 different process technologies ranging from 180nm to 32nm. Targeted at mobile and high-volume consumer applications … Read More → "Synopsys unveils 30 percent smaller area, low power USB 2.0 PHY IP for 28nm processes"

EVE-USA General Manager, unEVErsity Connections Program Manager

Will Attend Workshop to Discuss Program, Present ZeBu Emulation Platform

SAN JOSE, Calif.–(BUSINESS WIRE)–EVE, the leader in hardware/software co-verification, is a platinum sponsor of the IEEE International High-Level Design, Validation and Test (HLDVT) Workshop 2009 to be held November 4-6 at the Grand Hyatt Hotel in San Francisco.

Lauro Rizzatti, general manager of EVE-USA, and Sandra Larrabee, manager of the unEVErsity Connections Program, will be available to discuss the program that provides schools access to its advanced verification technologies and methodologies. Rizzatti will … Read More → "EVE Becomes Platinum Sponsor of IEEE International High Level Design, Validation and Test Workshop 2009"

Broad DesignWare audio IP portfolio shipped in more than 100 million units

MOUNTAIN VIEW, Calif.—October 28, 2009— Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of its 40th audio codec IP with the release of the DesignWare(r) 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process. Synopsys has been a leading provider of audio IP for more than twelve years and provides designers with high-quality audio IP solutions supporting 20 different process nodes, from 180-nanomenter (nm) to 65-nm processes and with performance … Read More → "Synopsys announces 40th DesignWare audio codec IP"

Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production

MOUNTAIN VIEW, Calif.—October 28, 2009— Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that NVIDIA Corp. has adopted Synopsys’ Yield Explorer solution for yield analysis and yield ramp. NVIDIA, which invented the graphics processing unit, selected Yield Explorer because of its ability to coherently combine and cross-correlate large volumes of data from the design, fab and test domains to quickly identify dominant failure mechanisms. This … Read More → "NVIDIA adopts Synopsys Yield Explorer to reduce time to volume"

SystemVerilog Analyzer, Static Elaborator Serve as Front End to New Synthesis Software for Asynchronous Chip Design

ALAMEDA, Calif.–(BUSINESS WIRE)–Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual property (IP) for embedded applications, has chosen Verific Design Automation, a de facto industry standard, as the front end for its software products.

Tiempo licenses Verific’s SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog.

“Verific’s software … Read More → "Tiempo Chooses Verific Design Automation’s SystemVerilog Front End"

MILPITAS, SUNNYVALE and FREMONT, Calif., Oct. 27 /PRNewswire/ — Open-Silicon, Inc., MIPS Technologies, Inc. (NASDAQ:MIPS) , and Virage Logic (NASDAQ:VIRL) today announced the co-development of test chips showcasing the companies’ industry-leading technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the fastest processors built in a 65nm ASIC. Also, work has begun on a follow-on 40nm device targeting frequencies in excess of 2.5GHz and providing over 5000 DMIPS of performance. Both efforts utilize Open-Silicon’s CoreMAX(TM) technology as well as the superscalar MIPS32& … Read More → "Open-Silicon, MIPS Technologies, and Virage Logic Achieve High Performance ASIC Processor Design 65nm Silicon Runs 1.1GHz Today; 40nm Target to Exceed 2.5GHz"