New Lattice FPGA Design Tool Suite Includes Advanced Support For High Performance DDR Interfaces
— Version 8.0 Software Helps Build High Speed, Robust, Double Data Rate Interfaces —
HILLSBORO, OR — NOVEMBER 10, 2009 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 8.0 of its ispLEVER® FPGA design tool suite, which includes many enhancements for the design of high speed double data rate (DDR) interfaces for the LatticeECP3™ FPGA family. These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.
“Although our ECP3 FPGA family probably is best known for its low … Read More → "New Lattice FPGA Design Tool Suite Includes Advanced Support For High Performance DDR Interfaces"