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CoFluent Design and No Magic Deliver The World’s First Industrial Grade UML To SystemC Solution For Multicore System Simulation

Paris, France and Plano, Texas – FEBRUARY 17, 2010 – CoFluent Design™, a leading Electronic System Level (ESL) company that provides system-level modeling and simulation to accelerate innovation in embedded devices,Read More → "CoFluent Design and No Magic Deliver The World’s First Industrial Grade UML To SystemC Solution For Multicore System Simulation"

EU funded microelectronics project launched to enhance lithography-based yield

Copenhagen, Denmark, February 17, 2010 — Supported by funding from the European Union’s Seventh Framework Programme, a consortium of eight leading institutions has launched a joint microelectronics research project aiming to develop innovative design methods and related EDA tools which remove the limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography. The Synaptic consortium is composed of eight leading institutions, including four European technology companies, a European world-leading research institute in the field of nanoelectronics, and three academic institutions, two from Europe and one from … Read More → "EU funded microelectronics project launched to enhance lithography-based yield"

Agilent Technologies’ New LTE Applications Target 4G System-Level Designers

SANTA CLARA, Calif., Feb. 16, 2010 – Agilent Technologies Inc. (NYSE: A) today introduced a new line of system-level design and verification products for 3GPP LTE physical layer (PHY) design at Mobile World Congress 2010. In addition to its traditional test and measurement products, Agilent now provides predictive products and algorithmic references for the SystemVue platformthat are consistent with the LTE v.8.9.0 (December 2009) standard. The new line includes four products that accelerate 4G deployment for LTE system architects, baseband hardware designers, and RF equipment by … Read More → "Agilent Technologies’ New LTE Applications Target 4G System-Level Designers"

Yamaha tapes out its latest Graphics LSI Chip with Synopsys Design Compiler Graphical

MOUNTAIN VIEW, Calif., February 9, 2009 —Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Yamaha, a leading provider of mobile audio and Graphics LSI chip products, achieved their aggressive performance targets ahead of schedule with Design Compiler® Graphical and successfully taped out their latest Graphics LSI chip. Traditionally, time-consuming iterations between synthesis and place-and-route have been performed due to routing congestion issues identified by the backend design teams late in the design. Design Compiler Graphical predicts and removes routing congestion early in the design flow during … Read More → "Yamaha tapes out its latest Graphics LSI Chip with Synopsys Design Compiler Graphical"

OrCAD Market Reach Expanded With Additional Allegro Technology

Rochester, NY (February 9, 2010) – EMA Design Automation™ (www.ema-eda.com), one of the world’s largest Electronic Design Automation Value Added Resellers, today announced some changes to the part number schema with the new Cadence® Design Systems Allegro® and OrCAD® 16.3 release. These changes enhance the breadth of technology available … Read More → "OrCAD Market Reach Expanded With Additional Allegro Technology"

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