HSINCHU, Taiwan, June 7 /PRNewswire-FirstCall/ — Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today extended its Open Innovation Platform™ with another focus on system-level design, analog/mixed-signal (AMS)/RF design and two-dimensional/three-dimensional integrated circuit (2-D/3-D IC) implementation. At the same time the company introduced the first three initiatives from the new focus. 

TSMC originally launched the Open Innovation Platform in 2008 as an industry-wide design enablement initiative. To date, the Open Innovation platform has accelerated time-to-market, improved return on design investment and reduced design infrastructure duplication. It includes a set of interoperable ecosystem interfaces, collaborative … Read More → "TSMC Extends Open Innovation Platform™"

MOUNTAIN VIEW, Calif. – June 7, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the industry’s advancing process technology and design needs. IMTAB founding members include representatives from industry-leading … Read More → "Synopsys and IEEE-ISTO launch an industry wide technical advisory board to evolve Interconnect Modeling Standard"

SANTA CLARA, Calif., June 3 /PRNewswire/ — Tabula, Inc., a privately held fabless semiconductor company and developer of the ABAX family of 3-D Programmable Logic Devices (3PLDs), will be demonstrating its 40nm ABAX product family at the Design Automation Conference held June 13-18th in Anaheim, California at the TSMC Booth #294. Tabula will exhibit with its IP partner, Analog Bits, Inc., the global market leader in providing customized transistor level IP components for CMOS logic processes and who developed the PMA portion of the physical layer SERDES, PLLs, DLLs, and I/Os embedded in ABAX.

At the TSMC … Read More → "Tabula to Demonstrate the ABAX 40nm, 48-Channel, Multi-protocol 6.5Gbps SERDES at DAC 2010"

SUNNYVALE, CALIFORNIA / LANDSHUT, GERMANY – June 4, 2010 –  Nangate, the leading supplier of digital cell library development and design optimization solutions, and LFoundry, the dedicated analog, mixed signal and … Read More → "Nangate announces integration of OpenAccess database for Library Creator™ Platform into LFoundry’s advanced LF150 PDK"

MOUNTAIN VIEW, Calif., June 3, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing today announced that its Synphony HLS (High Level Synthesis) product now includes optimised support for Xilinx Virtex®-6 FPGAs. The high level synthesis flow provides Virtex-6 FPGA users with more automatic target-specific optimisations and architecture exploration from high level models and delivers up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications.

The Synphony HLS product generates optimised RTL for Virtex-6 FPGA implementation as well as testbench … Read More → "Synopsys announces Synphony HLS support for Xilinx Virtex-6 FPGAs"

TORONTO –– June 3, 2010 –– Read More → "Vennsa Technologies Sets Sights on Moving Chip Verification Beyond Debug"

SANTA CLARA, CALIF. –– June 2, 2010 –– Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips.

Read More → "Juniper Networks Selects RealTime Designer from Oasys for Next-Generation Networking Chip Designs"

THAME, United Kingdom, May 24, 2010 – Imperas today announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded™ software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus … Read More → "Imperas Eases Embedded Software Development With Mentor Graphics Nucleus RTOS and EDGE Development Tools"

May 27th 2010, Uppsala, Sweden. IAR Systems today announced the launch of their new RTOS & Middleware Partner Program for IAR Embedded Workbench. By selecting some of the best and most recognized RTOS products from around the world, the Program will provide a broad and comprehensive development tools ecosystem of RTOS and middleware products, all highly integrated with IAR Embedded Workbench.

Current companies have been selected for the program are: CMX, eForce, Express Logic, FreeRTOS, Micrium, Micro Digital, Quadros, Sciopta, SEGGER and Wittenstein. New partners may be added in the future.

With the growing usage of 32 … Read More → "Leading RTOS & middleware companies integrate with IAR Embedded Workbench to become part of unique development tools ecosystem"

Albuquerque, New Mexico, May 2010 – Innovasic Semiconductor’s new web-based Developer Portal provides access to a complete Industrial Ethernet design solution that includes development tools and personalized technical support. The portal is a secure and private workspace with tutorials, design and conformance testing resources, online access to evaluation hardware, comprehensive FAQs, and direct technical support.  Having these resources in one place allows designers to quickly assess and integrate an Industrial Ethernet interface into their product.Read More → "New Developer Portal Supports Fast Integration of Industrial Ethernet Interfaces"