San Jose, Calif. – August 30, 2010 – S2C Inc., a rapid SoC prototyping provider, announces the release of its fourth-generation rapid SoC prototyping tool, V6 TAI Logic Module, based on Xilinx’s 40-nm Virtex™ field-programmable-gate-array (FPGA).
Each … Read More → "S2C Announces Virtex-6 Based 4th Generation Rapid SoC Prototyping Solution"
WILSONVILLE, Ore., August 26, 2010—Mentor Graphics Corporation (NASDAQ: MENT) today announced it has collaborated with GLOBALFOUNDRIES to create a facility called Graphical Design Rule Manual (GDRM) that helps IC designers rapidly debug layout design rule violations by integrating the Calibre® RVE™ results viewing environment with GLOBALFOUNDRIES’ electronic design rule manuals. With GDRM, designers using the Calibre RVE tool to correct DRC hotspots can automatically access detailed GLOBALFOUNDRIES textual and graphical reference information about the specific rules generating the violations. By providing instant access to relevant information, the solution allows designers to fix errors more quickly and … Read More → "Mentor Graphics Collaborates with GLOBALFOUNDRIES to Provide Easier Debugging Capability to IC Designers"
MOUNTAIN VIEW, Calif., Aug. 25 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Global Unichip Corporation (GUC) has achieved first-pass silicon success for its GP5080 Solid State Drive (SSD) system-on-chip (SoC) utilizing the complete Synopsys DesignWare® SATA IP solution, consisting of controller, PHY and verification IP. GUC, a leading full-service SoC design foundry, determined that Synopsys’ DesignWare SATA IP was superior in quality, power consumption, performance and feature … Read More → "Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation"
MOUNTAIN VIEW, Calif., Aug. 24 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced immediate availability of the DesignWare® MIPI M-PHY® IP for next-generation high-speed interfaces based on the newly ratified MIPI® Alliance M-PHY specification. With this latest addition to the DesignWare MIPI IP portfolio, Synopsys is the first provider to offer a comprehensive solution of a controller and PHY IP for both the MIPI DigRF(SM) v3 (2.5 … Read More → "Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology"
Belgrade, Serbia – August 23rd, 2010 – HDL Design House has announced the VITAL HVT M25PX behavioral simulation model for Numonyx M25PX16, a 16 Mbit (2 Mb x 8) serial flash … Read More → "HDL Design House announces HVT M25PX VITAL behavioral model"
MOUNTAIN VIEW, Calif., Aug. 23 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced it will be hosting its first Synposium, a virtual trade show event where attendees around the world can learn about Synopsys’ EDA software, IP, prototyping and services from the convenience of their desks. During the first three days of the event, Synopsys staff will be available to chat online in this interactive online format. Synposium attendees can view the materials on-demand through December 3, 2010.
What: Synopsys Synposium, a Virtual Event
… Read More → "Synopsys to Host First Synposium Virtual Event"
San Jose, California – August 16, 2010 – InPA Systems, Inc. has been formed to develop and market FPGA-based rapid prototyping technology that allows users to … Read More → "InPA Systems Inc. Targets Active Debug™ for Rapid Prototyping"
NEW YORK –– August 17, 2010 –– Luca Daniel, Emanuel E. Landsman associate professor of Electrical Engineering at Massachusetts Institute of Technology, has been chosen as this year’s recipient of the Early Career Award from the IEEE Council on Electronic Design Automation (CEDA).
Professor Daniel will be recognized for his contribution to electromagnetic field analysis, parasitic variation-aware extraction and automated parameterized linear and non-linear stable model reduction during ICCAD’ … Read More → "IEEE Council on EDA to Honor MIT’s Luca Daniel with Early Career Award"
HILLSBORO, OR — AUGUST 16, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.4 of its ispLEVER® Classic design tool suite. The ispLEVER Classic design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH® 4000ZE CPLD fitter with improved power optimization.
Synplify Pro HDL Analyst provides designers a way to rapidly visualize high-level register transfer level (RTL) Verilog or VHDL. Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is … Read More → "Lattice Announces Improved Synthesis And Power Optimization in CPLD Tools"
MOUNTAIN VIEW, Calif. – August 12, 2010 — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the launch of the DesignWare® USB Software Alliance Program with leading USB software providers emsys, Jungo, MCCI and MicroDigital as inaugural members. This alliance program establishes an ecosystem of qualified USB software providers for drivers, firmware and stacks which have proven interoperability with Synopsys’ DesignWare USB 2.0 and SuperSpeed USB 3.0 IP. Synopsys and its DesignWare USB Software Alliance Program members can help designers to quickly incorporate USB connectivity into their system-on-chips (SoCs) with … Read More → "Synopsys launches DesignWare USB software alliance program"
