MONROVIA, California – September 14, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), has joined the IPL Alliance, an industry organization established to develop an interoperable eco-system for custom design by creating and promoting interoperable process design kit (iPDK) standards. Tanner EDA provides analog and mixed-signal (A/MS) designers with the Read More → "Tanner EDA Joins IPL Alliance to Widen Adoption of Interoperable Process Design Kits for Analog/ Mixed-signal Designs"

Eindhoven, The Netherlands,  September 14, 2010. Huntron, Inc., a leader in PCB diagnosis and troubleshooting equipment for over 30 years, and JTAG Technologies, a tier one supplier of boundary-scan products world-wide, today announced the integration of their test methods within Huntron’s range of prober enhanced analog signature analysis products.

‘Huntron Tracker’ is synonymous with PCB fault detection using the technique known as analog signature analysis. From today users of this technology can now take advantage of advancements made in the digital world that allow PCBs to be tested using built-in logic … Read More → "Boundary-scan Boost for Huntron Robotic Probers"

MOUNTAIN VIEW, Calif., Sept. 14 /PRNewswire/ — Synopsys, Inc. (NASDAQ: SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that eMemory Technology, Inc. has selected Synopsys’ CustomSim(TM) solution for all of its circuit simulation needs. On a 45-nanometer (nm) embedded non-volatile memory, the CustomSim solution demonstrated up to 2 times faster simulation runtime compared to other commercial FastSPICE tools, and delivered results tightly correlated to silicon data. Based on these results, CustomSim is now used in verification … Read More → "eMemory Standardizes on Synopsys FastSPICE for Circuit Simulation"

SAN FRANCISCO, Sept. 10 /PRNewswire/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, will be demonstrating its complete DesignWare® IP solutions for PCI Express® 3.0, USB 3.0 and SATA 6 Gb/s, consisting of device, host, PHY and verification IP, at the Intel Developer Forum (IDF) in San Francisco, California from September 13-15.

IDF is the premier global technology industry event bringing together technology professionals who are actively directing where technology is going. … Read More → "Synopsys Showcases DesignWare IP Solutions for PCI Express, USB and SATA at Intel Developer Forum 2010"

Northwich, Cheshire, 2^nd September 2010. Kane Computing Ltd (KCL), today announced that the popular Impulse C to FPGA tool set, that they sell in the UK has now been integrated to Stone Ridge Technology products. The integration enables software developers to write HLL (High Level Language) signal, imaging or data processing algorithms that rapidly compile to optimized … Read More → "C-to-FPGA Integration Accelerates DSP Prototyping by ten"

MOUNTAIN VIEW, Calif. – September 07, 2010 – CEVA, Inc. [(NASDAQ: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643™, a  highly-energy efficient,1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to … Read More → "CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs"

Oslo, Norway, September 2, 2010 – Energy Micro®, the energy efficient microcontroller company, has introduced a free software tool designed to remove the traditionally time-consuming problem of debugging I/O pin conflicts.  Supporting the complete EFM32 Gecko low power MCU family, energyAware Designer ensures correct pin configuration and automatically generates set-up code and documentation.

On creating a new project, designers select a target MCU and are presented with a default device configuration.  Clicking on a peripheral function enables it and highlights respective pins in green on an intuitive pin-out diagram.  Pin-conflicts induced by selecting another peripheral, … Read More → "Energy Micro tool instantly resolves MCU pin conflicts"

Starnberg, August 31, 2010 – qaqadu event gmbh, expert for technical education, again offers technical short courses on engineering topics starting in October 2010. Thus meeting the further increasing demand for information on topics such as digital signal processing and FPGAs (Field Programmable Gate Arrays), qaqadu will present the following courses: FPGAs for embedded processors (October 12-14, 2010). DSP for FPGAs (November 16-19, 2010), and DSP Theory, Algorithms and Architectures (December 7-10, 2010). The courses are going to take place in Munich, Germany. The instruction language is English.

Special attention is paid to practical experience; after each presentation a hands-on session will follow in … Read More → "Technical Education on Digital Signal Processing, FPGAs and Embedded Processors"

About IO Checker 

IO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins.

Read More → "HDL Works Presents ‘IO Checker 2.0’"

Shanghai, China – Aug 27^th, 2010 – SoCIP 2010 Road Show seminars will be making stops at Shenzhen on Sep 7^thRead More → "SoCIP Road Shows to Stop at Shenzhen, Chengdu and Xi’an"