SANTA CLARA, Calif., Oct. 15, 2010 — Agilent Technologies Inc. (NYSE:A – News) today introduced the Agilent 53200 RF and universal frequency counter/timer series, the first frequency counters with LXI Class C compliance.

The 53200 series, featuring industry-leading performance and usability, is built with standard computing I/O for ease of connectivity and data collection. The combination of high-speed … Read More → "Agilent Technologies Introduces Industry’s First LXI RF and Universal Frequency Counter/Timers"

Campbell, CA – October 14, 2010 – Silicon Frontline Technology, Inc. (SFT) an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that its software has been used to accurately verify over 250 electronic designs to date. The company now has over 25 customers, who use its software to analyze power devices, nanometer and Analog Mixed Signal (A/MS) designs. This list includes 10 of the world’s top 30 semiconductor companies. In addition, leading foundries have validated Silicon Frontline’s products … Read More → "Silicon Frontline Continues on Path to Success, Verifies Hundreds of Designs with Its Post-Layout EDA Software"

WILSONVILLE, Ore., October 15, 2010—Mentor Graphics Corporation (NASDAQ: MENT) today announced that NVIDIA has adopted the Olympus-SoC™ product for multi-corner, multi-mode (MCMM) design closure of their high performance graphics processors. The Olympus-SoC system significantly reduces time to market while improving quality of results with advanced design closure capabilities like synchronized optimization, interconnect re-synthesis and physical SDC, in addition to MCMM closure for very large designs.

“We build some of the world’s largest and highest performance ICs and it’s crucial for us to maintain design schedules in the face of increasing IC … Read More → "NVIDIA Uses Mentor’s Olympus-SoC Place and Route System for Leading-Edge Graphics Processors"

San Francisco, October, 14 2010 – EE Times Group, a UBM company and the daily source of essential business and technical information for the electronics industry’s decision makers, today announced the conference program for DesignCon, historically the season opening event for the electronics design community. The annual conference and trade show begins January 31st at the Santa Clara Convention Center, Santa Clara, CA, and runs through February 2nd, with the companion Exhibition running February 2nd and 3rd. Agilent Technology has been named the event’s Host Sponsor, and will be holding a half-day educational forum on January 31st … Read More → "Calling all Chipheads: DesignCon Announces 2011 Program"

WILSONVILLE, Ore., October 13, 2010—Mentor Graphics Corporation (NASDAQ: MENT) today announced the Inflexion Platform™ User Interface (UI) for Android, a comprehensive development toolkit comprising a graphics engine and UI creation tool that enables Android application developers to rapidly customize product UIs with visually compelling 2D and 3D animated elements for increased product differentiation.

The Inflexion Platform UI for Android is ideal for smart phones and consumer devices where product differentiation is critical, and for non-smart phone Android and Linux-based devices, such as televisions, set-top boxes, printers, infotainment systems, and other products which would otherwise require significant … Read More → "Mentor Graphics Announces Inflexion Platform User Interface (UI) for Android-Based Device Development"

Belgrade, Serbia, October 13^th, 2010 – HDL Design House has announced today the availability of the HIPA 21000, a high performance low cost serializer-deserializer (SerDes) meant to be used in the systems based on Serial RapidIO protocol. It can also be used with any protocol that supports 8b/10b encoding and similar baud rates as Rapid IO serial protocol. Serial data transfer rate is to be chosen between five different values: 1.25Gbaud/s, 2.5Gbaud/s, 3.125Gbaud/s, 5Gbaud/s, 6.25Gbaud/s. 

< … Read More → "HDL Design House announces high performance serializer deserializer (SerDes) for Serial Rapid IO protocol 2.1 (HIPA 21000) IP core"

MOUNTAIN VIEW, Calif., Oct. 13 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that GSI Technology, a leader in high-density, high-speed monolithic SRAMs, has selected Synopsys’ CustomSim™ FastSPICE solution for the development and verification of its leading-edge designs. GSI Technology’s 144-megabit (Mbit) SigmaQuad SRAMs achieve data bandwidths in excess of 72 gigabits per second (Gbps). In order to maximize yield with such aggressive timing specifications, extensive full-chip transistor-level simulations need to be run over multiple process, voltage and temperature corners. CustomSim delivered confirmed silicon-accurate results while simulating … Read More → "Synopsys CustomSim Selected by GSI Technology for High-Speed SRAM Simulation"

SUNNYVALE, Calif. – October 12, 2010 – MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced that it has joined the TSMC (TWSE: 2330, NYSE:TSM) Soft IP Alliance Program to speed customers’ time-to-market. Through the Soft IP Program, TSMC is expected to provide specific design documents and technology information so that MIPS and other Alliance partners can optimize IP cores for TSMC’s process technologies. The companies will also collaborate on roadmap alignment to expedite … Read More → "MIPS Technologies Joins TSMC IP Alliance to Speed Customers’ Time-to-Market"

Eindhoven, the Netherlands, October 2010. JTAG Technologies is delighted to announce a new economically-priced software and hardware system for board-level and system designers looking to benefit from a boundary-scan test and programming strategy.

Boundary-scan, or JTAG, testing has remained a powerful tool for identifying assembly faults such as open- and short-circuits, missing components and damaged devices since its introduction (as IEEE Std 1149.1) in 1990. However, while boundary-scan tools have been in use for almost 20 years, the relatively high cost of ‘professional’ systems has meant that they largely remain in the domain … Read More → "Full-featured Value Boundary-scan Developers Suite"

MOUNTAIN VIEW, Calif., Oct. 12 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its award-winning Galaxy™ Implementation Platform product, IC Validator, for In-Design physical verification within IC Compiler, has been successfully used for more than 100 tapeouts at advanced process nodes. Coming so soon after IC Validator’s 2009 launch, this milestone is a strong indicator of the requirement for a different physical verification use model. In contrast to the traditional stand-alone physical verification approach performed at the end of the design cycle, the new In-Design approach is … Read More → "100 Tapeouts Underscore Rapid and Broad Acceptance of Synopsys’ In-Design Physical Verification"