SANTA CLARA, Calif., Nov. 15, 2010 — Agilent Technologies Inc. (NYSE: A) today announced that its IC-CAP Wafer Professional (WaferPro) software has been successfully deployed at STMicroelectronics. WaferPro adds new capabilities toAgilent’s Integrated Circuit and Analysis Program (IC-CAP) software platform to enable efficient, automated on-wafer measurements for device modeling applications.

STMicroelectronics uses IC-CAP as a device modeling platform to extract semiconductor device models for silicon devices (CMOS and BJT, for example). … Read More → "Agilent Technologies’ Software Fundamentally Improves, Automates STMicroelectronics’ Device Modeling On-Wafer Measurements"

NEW ORLEANS, LA–(Marketwire – November 15, 2010) – Today at SuperComputing 2010, Rogue Wave Software, Inc., a Battery Ventures portfolio company, announced the general availability of IMSL Fortran Numerical Library version 7.0. This release of the company’s powerful math and statistics algorithms will allow users with supported hardware to simply link the IMSL Fortran Library with NVIDIA’s CUDA BLAS to gain the significant performance improvement available by offloading processing to the GPU.

“We are pleased to see the IMSL Fortran … Read More → "Rogue Wave Software Releases Version 7.0 of the IMSL® Fortran Numerical Library With Additional Algorithms and Support for NVIDIA CUDA"

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today introduced a new holistic approach to Silicon Realization that moves chip development beyond a patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. This approach represents a stark turn from the discreet and compartmentalized ways semiconductor and systems companies have traditionally achieved Silicon Realization, the term that refers to all the steps required for bringing a design to silicon and a key component of … Read More → "Cadence Unveils Holistic Approach to Silicon Realization"

BANGALORE, INDIA–(Marketwire – November 15, 2010) – Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence® Silicon Realization product line. Open-Silicon completed the entire design using Cadence’s integrated end-to-end Encounter® digital design, implementation, and manufacturability signoff technology.

“Cadence offers a complete suite of tools for … Read More → "Open-Silicon Achieves Ultra High Performance Using Cadence Silicon Realization Technology to Tape-Out Breakthrough 2.4 GHz ASIC Processor"

MOUNTAIN VIEW, Calif. and SHANGHAI, Nov. 15, 2010 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981), today announced that they have delivered a comprehensive solution for system-on-chip (SoC) design for SMIC’s advanced 65-nanometer (nm) process. The solution integrates Synopsys’ broad DesignWare™ interface and analog IP portfolio plus other foundation IP with Synopsys’ Galaxy™ Implementation Platform, in a tuned reference flow. The companies have also begun work on their 40-nm design solution. Based on collaboration agreements for 65-nm and 40-nm, … Read More → "Synopsys and SMIC Team to Deliver Proven SoC Design Solution for 65-nm to 40-nm Process Nodes"

WHAT: Jasper Design Automation CEO Kathryn Kranen is an invited speaker at this year’s IP-SOC 2010, describing best practices for post-silicon validation, debug and verification, and offering timely solutions for this increasingly urgent issue.  Held annually in Grenoble, IP-SOC highlights IP-based SoC design issues with three days of seminars, panels and distinguished speakers.  2010 conference dates are Nov. 30 – Dec. 1.  For more information: http://www.design-reuse.com/ipsoc2010/.

WHEN:  Wednesday, Dec. 1, 10:30am-11:00 … Read More → "Jasper CEO Kathryn Kranen Addresses Post-Silicon Validation Challenge at IP-SOC 2010, Dec. 1, Grenoble"

MOUNTAIN VIEW, Calif., Nov. 11, 2010 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today reported that Cavium Networks, Inc. used NanoTime transistor-level static timing analysis (STA) solution to achieve full-chip STA signoff for its next-generation internet application processor, OCTEON II that is shipping now. The multi-core, high speed OCTEON II processor is optimized for high performance network packet processing and low power consumption. Targeted for scalable networking equipment designed to fuel the voice, video and data convergence driven by cloud computing, the OCTEON II required extremely accurate timing verification in … Read More → "Synopsys NanoTime Enables Full Chip Transistor Level Timing Analysis on Cavium Networks OCTEON II Internet Application Processor"

November 10, 2010, Woodcliff Lake, NJ — The USB Implementers Forum (USB-IF) has recently granted certification to the SuperSpeed USB 3.0 Device Controller IP Core from intellectual property provider CAST, Inc.

Certification by this standards body ensures the core satisfies the USB 3.0 specification and delivers the benefits of SuperSpeed USB: data transfer rates up to 5 Gbps, Sync-and-go technology to reduce wait times, reduced power consumption, and backwards compatibility with Hi-Speed USB 2.0.

While many … Read More → "SuperSpeed USB 3.0 IP Core from CAST, Inc. Achieves USB-IF Certification"