MOUNTAIN VIEW, Calif., June 14, 2010—Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced it is delivering an optimised, pre-validated design environment for the Common Platform alliance (CPA) 32/28 nanometer(nm) high-k metal gate (HKMG) technology based on Synopsys’ Lynx Design System. Accomplished under a multi-year collaboration with ARM and the Common Platform alliance [IBM, Samsung Electronics, Co., Ltd., GLOBALFOUNDRIES], the optimisations to the Lynx Design System and its Galaxy™ Implementation Platform-enabled flow for ARM’s advanced physical IP and the ARM Cortex™A9 MPCore … Read More → "Synopsys delivers optimised Lynx Design System for Common Platform 32/28nm technology"

MOUNTAIN VIEW, Calif., June 14 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and implementation of complex system-on-chips (SoCs). Today’s SoCs require libraries that contain hundreds of gigabytes of timing, power, noise and process variation data to ensure the chip meets all performance criteria. The Galaxy Characterization Solution is the only solution that can reduce the library size by an average of 4X and … Read More → "Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories"

MOUNTAIN VIEW, Calif., June 9, 2010— Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has collaborated with TSMC to validate Synopsys’ custom design solution with TSMC’s 28-nanometer (nm) interoperable process design kit (iPDK) and Analog/Mixed-Signal (AMS) Reference Flow 1.0. TSMC’s 28nm reference phase-locked loop (PLL) design was used to validate Synopsys’ comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0. The validated solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit … Read More → "Synopsys delivers comprehensive custom design solution for TSMC Analog/Mixed-Signal Reference Flow 1.0"

MOUNTAIN VIEW, Calif., June 09, 2010— Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it is delivering comprehensive design enablement for TSMC’s 28 nanometer (nm) process technology with TSMC Reference Flow 11.0. New features of the flow include solutions for system-level design and verification, added capabilities for 28-nm design, including In-Design physical verification, and support for thru-silicon via (TSV) technology for 3D IC design. Through Reference Flow 11.0, Synopsys tools and IP enable enhanced productivity, lower power, higher yield and increased performance and integration.

“TSMC and … Read More → "Synopsys delivers comprehensive design enablement for TSMC 28-nm process technology with Reference Flow 11.0"

Erfurt, Germany, June 8, 2010. X-FAB Silicon Foundries< … Read More → "X-FAB Announces 8-Inch MEMS Center for Cost-Effective, High-Volume, Advanced MEMS Production"

SAN JOSE, CALIF. –– June 8, 2010 –– EVE, the leader in hardware/software co-verification, … Read More → "During DAC, EVE to Highlight ZeBu’s Infinite Verification Possibilities, STMicroelectronics’ Use of ZeBu"

HSINCHU, Taiwan, June 8 /PRNewswire-FirstCall/ — Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today introduced Reference Flow 11.0 and Analog/Mixed Signal (AMS) Reference Flow 1.0. Both are key collaborative components of TSMC’s recently-announced extension of its Open Innovation Platform™.

Reference Flow 11.0, focuses on Electronic System Level (ESL) design, SoC Interconnect Fabric, and two dimensional and three dimensional integrated circuits (2-D/3-D ICs) using through silicon via (TSV) technology.  AMS Reference Flow 1.0 offers advanced multi-vendor AMS design flow fully integrated with an innovative TSMC AMS design package to manage the growing complexity of process effects as well … Read More → "TSMC Unveils Two New Reference Flows"

HSINCHU, Taiwan, June 7 /PRNewswire-FirstCall/ — Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today extended its Open Innovation Platform™ with another focus on system-level design, analog/mixed-signal (AMS)/RF design and two-dimensional/three-dimensional integrated circuit (2-D/3-D IC) implementation. At the same time the company introduced the first three initiatives from the new focus. 

TSMC originally launched the Open Innovation Platform in 2008 as an industry-wide design enablement initiative. To date, the Open Innovation platform has accelerated time-to-market, improved return on design investment and reduced design infrastructure duplication. It includes a set of interoperable ecosystem interfaces, collaborative … Read More → "TSMC Extends Open Innovation Platform™"

MOUNTAIN VIEW, Calif. – June 7, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the industry’s advancing process technology and design needs. IMTAB founding members include representatives from industry-leading … Read More → "Synopsys and IEEE-ISTO launch an industry wide technical advisory board to evolve Interconnect Modeling Standard"

SANTA CLARA, Calif., June 3 /PRNewswire/ — Tabula, Inc., a privately held fabless semiconductor company and developer of the ABAX family of 3-D Programmable Logic Devices (3PLDs), will be demonstrating its 40nm ABAX product family at the Design Automation Conference held June 13-18th in Anaheim, California at the TSMC Booth #294. Tabula will exhibit with its IP partner, Analog Bits, Inc., the global market leader in providing customized transistor level IP components for CMOS logic processes and who developed the PMA portion of the physical layer SERDES, PLLs, DLLs, and I/Os embedded in ABAX.

At the TSMC … Read More → "Tabula to Demonstrate the ABAX 40nm, 48-Channel, Multi-protocol 6.5Gbps SERDES at DAC 2010"