TORONTO –– June 3, 2010 –– Read More → "Vennsa Technologies Sets Sights on Moving Chip Verification Beyond Debug"

SANTA CLARA, CALIF. –– June 2, 2010 –– Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips.

Read More → "Juniper Networks Selects RealTime Designer from Oasys for Next-Generation Networking Chip Designs"

THAME, United Kingdom, May 24, 2010 – Imperas today announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded™ software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus … Read More → "Imperas Eases Embedded Software Development With Mentor Graphics Nucleus RTOS and EDGE Development Tools"

May 27th 2010, Uppsala, Sweden. IAR Systems today announced the launch of their new RTOS & Middleware Partner Program for IAR Embedded Workbench. By selecting some of the best and most recognized RTOS products from around the world, the Program will provide a broad and comprehensive development tools ecosystem of RTOS and middleware products, all highly integrated with IAR Embedded Workbench.

Current companies have been selected for the program are: CMX, eForce, Express Logic, FreeRTOS, Micrium, Micro Digital, Quadros, Sciopta, SEGGER and Wittenstein. New partners may be added in the future.

With the growing usage of 32 … Read More → "Leading RTOS & middleware companies integrate with IAR Embedded Workbench to become part of unique development tools ecosystem"

Albuquerque, New Mexico, May 2010 – Innovasic Semiconductor’s new web-based Developer Portal provides access to a complete Industrial Ethernet design solution that includes development tools and personalized technical support. The portal is a secure and private workspace with tutorials, design and conformance testing resources, online access to evaluation hardware, comprehensive FAQs, and direct technical support.  Having these resources in one place allows designers to quickly assess and integrate an Industrial Ethernet interface into their product.Read More → "New Developer Portal Supports Fast Integration of Industrial Ethernet Interfaces"

NEW YORK –– May 25, 2010 –– Steve Teig, president and chief technology officer (CTO) of Tabula, will describe an approach to move beyond von Neumann computing during a luncheon hosted by the IEEE Council on Electronic Design Automation (CEDA) at the 47th Design Automation Conference (DAC). 

Read More → "Tabula’s CTO Steve Teig to Speak During DAC Luncheon Hosted by IEEE’s Council on EDA"

SAN JOSE, Calif., May 25 /PRNewswire/ — D2S™, an emerging supplier of computational design platforms, today announced that Aki Fujimura, chairman and CEO of the company, will participate in a 22-nm manufacturing panel during the 47th Design Automation Conference (DAC) at the Anaheim Convention Center in Anaheim, Calif. DAC is the world’s leading technical conference and tradeshow covering the latest trends in electronic design and design automation, and will be held June 13-18. Aki Fujimura will participate in the Pavilion Panel “Hogan’s Heroes: What Design and Lithography Nightmares will 22nm Bring?” under the topic “New and Emerging … Read More → "D2S CEO Aki Fujimura to Participate in 22-nm Manufacturing Panel at DAC 2010"

Porto, Portugal/Edinburgh, UK — May 24^th 2010 — SILICONGATE LDA, a specialized supplier of Power Management … Read More → "Wolfson Selects SiliconGate to Supply Power Management IP for its Next Generation of High-Performance Products"

Who/What

EdXact, post-layout verification specialist < … Read More → "EdXact to Enhance Interactive Debugging Capabilities, Hierarchical File Handling and Improved Selectivity Features to Its Post-Layout Analysis Tools at 47th DAC"

SAN JOSE, CALIF. –– May 19, 2010 –– Forte Design Systems today launched Cynthesizer Ultra™, its high-level SystemC synthesis software tightly integrated with its CellMath product family to create better designs faster.& … Read More → "Forte Unveils Cynthesizer Ultra, Next-Generation High-level Synthesis"