NextOp Software Selects Verific Design Automation SystemVerilog
ALAMEDA, CALIF. –– January 20, 2011 –– Verific Design Automation today said that NextOp Software, Inc. has licensed its software for use with the NextOp assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability.
NextOp Software tightly integrated Verific’s SystemVerilog parser and static and register transfer level (RTL) elaborators with BugScope assertion synthesis, a tool that synthesizes high-quality assertions and functional coverage properties … Read More → "NextOp Software Selects Verific Design Automation SystemVerilog"