News – Page 2084 – EEJournal

Altera, MIPS Technologies and SLS Announce the MP32 Core, the First MIPS-Based, FPGA-Optimized Soft Core Processor

May 2, 2011

San Jose, Calif., May 2, 2011—Altera Corporation (NASDAQ: ALTR), MIPS Technologies (NASDAQ: MIPS) and System Level Solutions (SLS) Corporation today introduced a MIPS-Based™, FPGA-optimized soft processor for use on Altera’s FPGA and ASIC devices. The MP32 processor is a MIPS® compatible applications class processor that inherits one of the largest ecosystems of software development tools and operating system support in the industry. The MP32 processor is the industry’s first FPGA-based soft processor supported by Wind River’s VxWorks RTOS and … Read More → "Altera, MIPS Technologies and SLS Announce the MP32 Core, the First MIPS-Based, FPGA-Optimized Soft Core Processor"

Lattice Announces 4 x 3.125Gbps SRIO Capability on the Mid-Range LatticeECP3 FPGA Family

May 2, 2011

HILLSBORO, OR – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the availability of a 4 x 3.125Gbps version of the Serial RapidIO 2.1, Level 1 endpoint core utilizing the award winning LatticeECP3™ FPGA family. This is an extension of the previously announced SRIO v2.1 core that originally supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. This core can be … Read More → "Lattice Announces 4 x 3.125Gbps SRIO Capability on the Mid-Range LatticeECP3 FPGA Family"

Raggedstone3 – Cyclone™ IV PCI Express Development Board

May 2, 2011

Raggedstone3 expands the concept of the highly successful Raggedstone family of development boards from Enterpoint. The new Raggedstone3 extends the family with an increase in PCI performance to over 800 Mbytes/s a significant over previous products in the range. The 4 lane PCI Express interface is supported by a hard core PCIe function within the Altera™ Cyclone™ IV FPGA that is the heart of the board. </ … Read More → "Raggedstone3 – Cyclone™ IV PCI Express Development Board"

ClioSoft to Unveil Hierarchical Visual Design Diff at CDNLive! EMEA 2011

May 2, 2011

FREMONT, Calif., May 2, 2011 – ClioSoft, Inc., developer of the premier hardware configuration management (HCM) solutions for the electronics design industry, will demonstrate its SOS Design Collaboration Platform and Visual Design Diff with seamless integration with the Cadence® Virtuoso® custom design platform at CDNLive! EMEA 2011. Visual Design Diff (VDD) gives users the power to quickly compare two versions of a schematic or layout by graphically highlighting the … Read More → "ClioSoft to Unveil Hierarchical Visual Design Diff at CDNLive! EMEA 2011"

EEMBC® Delivers Android™ Support for CoreMark™ Embedded-Processor Benchmark

May 2, 2011

EL DORADO HILLS, Calif. — July 29, 2010 — The Embedded Microprocessor Benchmark Consortium (EEMBC) today announced Android porting support for its CoreMark 1.0 benchmark. This support enables CoreMark users to easily build and run CoreMark on any Android platform offering a native development kit (NDK). In testament to its widespread, international usage among engineers testing embedded processors, CoreMark downloads have exceeded 4000 in less than 2 years after its initial release.

From the start, EEMBC has made … Read More → "EEMBC® Delivers Android™ Support for CoreMark™ Embedded-Processor Benchmark"

MEMS Industry Group Offers Embedded Developers Inside Look at “Integrating MEMS with DSP/Microprocessors”

May 2, 2011

PITTSBURGH—May 2,2011—MEMS Industry Group (MIG), the trade association advancing micro-electromechanical systems (MEMS) across global markets, will moderate an industry panel on the challenges and benefits of integrating MEMS with DSP and microprocessors.

“Consumers are engaging with portable embedded systems in fundamentally new ways. They experience more realistic game play with Nintendo … Read More → "MEMS Industry Group Offers Embedded Developers Inside Look at “Integrating MEMS with DSP/Microprocessors”"

Isolated 12-Port Power over Ethernet PSE Controller Chipset Eliminates Optos for Lowest Solution Cost

May 2, 2011

MILPITAS, CA – May 2, 2011 – Linear Technology Corporation introduces the LTC4270/ LTC4271 isolated 12-port Power Source Equipment (PSE) controller chipset … Read More → "Isolated 12-Port Power over Ethernet PSE Controller Chipset Eliminates Optos for Lowest Solution Cost"

VIA Nano™ X2 E-Series Dual Core Processors Debut at Embedded System Conference

May 2, 2011

Taipei, Taiwan, April 29, 2011 – VIA Technologies, Inc, a leading innovator of power efficient x86 processor platforms, today announced that it will unveil its new family of low power dual core VIA Nano X2 Series processors at the Embedded System Conference, held at the McEnery Convention Center, San Jose from 2 – 5 May. The VIA booth is located at No 2032.

VIA Nano X2 E-Series processors combine a highly optimized, power-efficient dual-core architecture with advanced performance for the most demanding 86 … Read More → "VIA Nano™ X2 E-Series Dual Core Processors Debut at Embedded System Conference"

PRQA Introduces a New Approach to Defect and Security Vulnerability Detection

May 2, 2011

HERSHAM, UK, May 2 2011 / — PRQA | Programming Research today announced a new release of its industry leading QA·C product with sophisticated technology to perform deep-flow dataflow analysis. QA·C 8.0 identifies critical coding issues relating to control-flow, variable state and library usage.

“The embedded software industry, dominated by the use of C and C++ languages, welcomes our new dataflow analysis capability,” said Fergus Bolger, Chief Technical Officer at PRQA. “QA·C 8.0 overcomes a limitation of many current static analysis tools, since it focuses on detailed code semantics rather than abstracting summary … Read More → "PRQA Introduces a New Approach to Defect and Security Vulnerability Detection"

Veridae Systems Simplifies Validation and Debug of Complex FPGA-based Systems with the New Corus Suite

May 2, 2011

SAN JOSE, CA May 2, 2011 Veridae Systems today announced the Corus validation and debug software suite for complex FPGA-based systems. The Corus software suite is the first on the market to deliver a synchronized view of multi-FPGA systems both on- and off-chip, across devices and timing domains. With access to any observed signal, any time, designers and validation engineers can quickly pinpoint failures and fix root causes. The enhanced visibility delivered by Corus allows debug problems that previously required weeks, or even months, to be resolved in hours.