News – Page 2080 – EEJournal

Imagination brings long standing experience to successfully deliver DirectX for next generation Windows for SoCs

June 3, 2011

Taipei, Taiwan, June 2^nd 2011: Imagination Technologies, a leading multimedia and communications technologies company, is delivering graphics and video IP cores supporting the newest versions of Microsoft DirectX across x86 and ARM based SoCs (Systems on Chip) for the next version of Windows as well as on x86 Windows 7 PCs.

As the Windows platform drives the convergence of desktop and consumer appliances, Imagination has seen growing demand for DirectX capabilities and its market proven DirectX compatible POWERVR graphics and video hardware IP (Intellectual Property) cores, which form a fundamental enabling technology for that convergence … Read More → "Imagination brings long standing experience to successfully deliver DirectX for next generation Windows for SoCs"

Synopsys Collaborates With STMicroelectronics to Help Achieve Critical Milestone in 20-nm Design

June 3, 2011

MOUNTAIN VIEW, Calif., June 2, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced its close cooperation with STMicroelectronics (ST) in the successful tapeout of ST’s first 20-nanometer (nm) technology demonstrator test chip. This tapeout represents a critical milestone in the R&D collaboration between the two companies to develop a comprehensive design enablement solution for system-on-chip (SoC) integrated circuits (ICs) using ST’s next-generation 20-nm process technology, co-developed with its ISDA (International Semiconductor Development Alliance) partners in Fishkill, NY.

R&D teams from … Read More → "Synopsys Collaborates With STMicroelectronics to Help Achieve Critical Milestone in 20-nm Design"

ARM Cortex-A8, Cortex-A9 and Cortex-M4 OVP Fast Processor Models Provided by Imperas

June 3, 2011

OXFORD, United Kingdom, June 3, 2011 – Imperas, which is a member of the ARM Connected Community, has released its first models of the Cortex-A family of ARM processor cores. Models of the ARM Cortex-A series of cores, along with models of the Cortex-M series of cores, are now available from Open Virtual Platforms (OVP), including example virtual platforms incorporating the cores and support for the cores in Imperas’ advanced software development tools.

The OVP Fast Processor Models and example platforms are available from the Open Virtual Platforms website, www. … Read More → "ARM Cortex-A8, Cortex-A9 and Cortex-M4 OVP Fast Processor Models Provided by Imperas"

Concept Engineering Introduces Integrated Debugging Tool for Mixed-signal Design at DAC 2011

June 3, 2011

FREIBURG, Germany – June 2, 2011 – Design and verification engineers who work on complex analog/ mixed-signal (AMS) designs or who need to customize and integrate analog or digital IP building blocks into their system-on-chip (SoC) or integrated circuit (IC) designs will be able to assess a new analysis and debugging tool at DAC 2011. Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, etc.) as well as with different design languages and … Read More → "Concept Engineering Introduces Integrated Debugging Tool for Mixed-signal Design at DAC 2011"

Oasys Design Systems adds DFT Capabilities to Chip Synthesis

June 3, 2011

SANTA CLARA, CALIF. –– June 2, 2011 — Oasys Design Systems today announced that its Chip Synthesis™ platform, in use in production environments, now includes design for test (DFT) capabilities, further extending the fast speed and high capacity of Oasys’ RealTime Designer™ software.

This follows an earlier announcement that the Chip Synthesis platform supports chip-level power analysis and optimization, and has the ability to synthesize a design from the register transfer level (RTL) with UPF … Read More → "Oasys Design Systems adds DFT Capabilities to Chip Synthesis"

Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping

June 3, 2011

WILSONVILLE, Ore., May 31, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Catapult^® C high-level synthesis tool now supports the synthesis of transaction level models (TLM). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista™ platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms.

Expanding its full-chip synthesis technology, the Catapult … Read More → "Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping"

MathWorks HDL Tools add Xilinx FPGA Hardware Verification

June 2, 2011

MathWorks today announced the availability of EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench.

The introduction of FIL adds to the comprehensive set of HDL verification options that EDA Simulator Link supports for algorithms created in MATLAB and Simulink. FPGA-based verification provides significantly higher run-time performance than is possible with HDL simulators and increases confidence that the algorithm … Read More → "MathWorks HDL Tools add Xilinx FPGA Hardware Verification"

Mentor Graphics Announces New Capital Tools that Expand Coverage Beyond the Electrical Design Domain

June 2, 2011

INTEGRATED ELECTRICAL SOLUTIONS EXPO, Detroit, Mich., June 2, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) announced today a significant expansion of the company’s Capital® product suite. Already offering a powerful electrical system and wire harness design flow for the automotive, aerospace and defence industries, the Capital suite now includes three new products that extend that flow both upstream and downstream. With the introduction of new tools addressing configuration complexity, harness manufacturing and vehicle documentation … Read More → "Mentor Graphics Announces New Capital Tools that Expand Coverage Beyond the Electrical Design Domain"

EDA Newcomer Veridae Systems Lands on Annual What to See at DAC Report From Top Analyst Firm Gary Smith EDA

June 2, 2011

VANCOUVER, BC. –– June 1, 2011 –– Veridae Systems was named by top EDA analyst Gary Smith among the leading companies to visit at the 48th Annual Design Automation Conference, to be held in San Diego from June 5-10.

Veridae is a newcomer to the EDA market, having launched the Clarus Post Silicon Validation Suite last fall. Since, the company has added has added the Certus suite for pre-silicon ASIC multi-FPGA prototyping verification, and the Corus suite for multiFPGA based systems product validation. Veridae’s technology has filled a significant gap& … Read More → "EDA Newcomer Veridae Systems Lands on Annual What to See at DAC Report From Top Analyst Firm Gary Smith EDA"

NI Expands FPGA-Enabled NI FlexRIO Family for PXI With Six New I/O Modules

June 2, 2011

NEWS RELEASE – May 31, 2011 – National Instruments today introduced the expansion of its NI FlexRIO product line with six new adapter modules featuring FPGA-based reconfigurable I/O to deliver enhanced functionality for general-purpose automated test and high-speed digital communication. The NI FlexRIO family is the industry’s first commercial off-the-shelf (COTS) solution to provide engineers the flexibility of NI LabVIEW FPGA technology with high-speed, user-configurable I/O on the Read More → "NI Expands FPGA-Enabled NI FlexRIO Family for PXI With Six New I/O Modules"

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