industry news
Subscribe Now

New 1-slot 3U OpenVPX Backplane For 100GbE SOSA Development

Waterloo, Ontario — March 20, 2025 – Pixus Technologies, a provider of embedded computing and enclosure solutions, has announced a new 3U OpenVPX backplane in a 1-slot size with a VITA 67.3c cutout.   This backplane can support SOSA(R) aligned slot profiles such as the 14.6.11 and 14.9.2 that utilize RF and/or optical interfaces through the backplane.
The new backplanes support the higher performance MultiGig RT3 connectors which can accommodate 100GbE speeds.  Pixus can also connect one or multiple of these backplanes with it’s other development boards to meet a wide variety of configuration options.  The Pixus backplanes allow various SOSA aligned boards to be utilized and can support the use of Meritec™ VPX3 rear shrouds.
Pixus offers SOSA aligned backplanes, chassis and chassis managers.  The company also provides MIL ruggedized and outdoor versions of NI/Emerson software defined radios.
 
 About Pixus Technologies
Leveraging over 20 years of innovative standard products, the Pixus team is comprised of industry experts in electronics packaging. Founded in 2009 by senior management from Kaparel Corporation, a Rittal company, Pixus Technologies’ embedded backplanes and systems are focused primarily on  ATCA, OpenVPX, MicroTCA, and custom designs.    Pixus also has an extensive offering of VME-based and cPCI-based solutions.   In May 2011, Pixus Technologies became the sole authorized North and South American supplier of the electronic packaging products previously offered by Kaparel Corporation and Rittal.

Leave a Reply

featured blogs
May 23, 2025
"Latent Reflections" is a spooky art project where an artificial intelligence (AI) shares its thoughts on a custom-built display...

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
77,616 views