industry news
Subscribe Now

eSilicon to demonstrate silicon performance of its 7nm 56G long-reach SerDes at ECOC, September 24-26, 2018

Join us in Anritsu’s Booth, #408

San Jose, Calif.

eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will demonstrate the silicon performance of its 7nm 56G long-reach SerDes during ECOC in Rome, Italy on September 24-26.

What
7nm 56G long-reach SerDes demonstration
eSilicon will demonstrate the silicon performance of its 56G PAM4 SerDes by showing a periodic pattern generator (PPG)-to-chip live demo with different backplane reaches in the Anritsu Booth, #408. This is the first public demonstration of eSilicon’s 7nm SerDes technology showing one of its key features: high insertion loss tolerance with low bit-error rates to support increased bandwidth in legacy equipment.

The demonstration will show 56G PAM4 data transfer running at 56Gb/s over two different BERTSCOPE channels with two different reaches, both driven by the Anritsu MP1900A Signal Quality Analyzer-R using a passive and an active PAM4 combiner. The demo with Anritsu is significant because it will show how it is possible to leverage TX finite impulse response (FIR) capabilities to increase performance and improve power figure of merit (FOM) and functionality.

“To obtain such reach and effectively stress the PAM4 SerDes receiver, it is very important to be able to generate an original extremely high-quality signal, and include equalization and stress tools for full control of the TX side. During the bring-up period, a flexible solution like Anritsu’s MP1900A is the best choice for an interoperability test,” said Anritsu EMEA Wireline Marketing Director Alessandro Messina.

When
Monday-Wednesday, September 24-26, 2018

Where
ECOC Anritsu Booth, #408, Rome, Italy

About ECOC
ECOC is the leading European conference in the field of optical communication.

About Anritsu Corporation
Anritsu Corporation is a global provider of innovative communications test and measurement solutions for 120 years. Anritsu’s “2020 VISION” philosophy engages customers as true partners to help develop wireless, optical, microwave/RF, and digital solutions for R&D, manufacturing, installation, and maintenance applications, as well as multidimensional service assurance solutions for network monitoring and optimization. Anritsu also provides precision microwave/RF components, optical devices, and high-speed electrical devices for communication products and systems. The company develops advanced solutions for 5G, M2M, IoT, as well as other emerging and legacy wireline and wireless communication markets. With offices throughout the world, Anritsu has approximately 4,000 employees in over 90 countries.

About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
38,882 views