DVCon U.S. 2020 Offers Practicing Engineers Outstanding Technical Program

Louisville, CO— January 22, 2020—The 2020 Design and Verification Conference and Exhibition (DVCon) U.S., now in its 32nd year, has much to offer attendees over the course of the four-day program including 42 technical papers, four tutorials, 23 posters, 10 short workshops, two panels and a keynote address focused on artificial intelligence for design automation.

The program is now available online and advance registration is available through January 27. DVCon U.S., sponsored by Accellera Systems Initiative, will be held March 2-5, 2020 at the DoubleTree Hotel in San Jose, California.

“We are very proud of the technical program we’ve put together for attendees,” stated Vanessa Cooper, DVCon U.S. 2020 Technical Program Chair. “The technical program committee has been hard at work to provide an exciting conference that covers a broad range of subjects that are of great value to our audience. Topics throughout the program include automating verification solutions, portable stimulus, artificial intelligence, machine learning, IP security, SystemC, UVM strategies, and much more. There is no shortage of interesting sessions for attendees to choose from.”

Program Highlights include:

A tutorial, “Portable Stimulus: What’s Coming in 1.1 and What it Means for You” on Monday, March 2 presented by members of the Accellera Portable stimulus Working Group.
Six short workshops on Monday afternoon on topics including: IP Security Assurance, Dealing with Programmable IP, SystemC, System Level Design Flows, Security Verification and Parameterized RTL in a UVM Testbench. Four short workshops on Thursday afternoon on topics such as The Exascale Debug Challenge, HSI Issues, System RDL to PSS Basic to Pro, and Closing and Creating GAPS Between Design and Verification. The short workshop format allows attendees more access to in-depth presentations on a wide variety of topics in a 90-minute format.
A thought-provoking keynote address, “Artificial Intelligence for Design Automation,” on Tuesday, March 3 from 1:30pm-2:30pm in the Oak/Fir Ballroom presented by Dr. Anirudh Devgan, president of Cadence Design Systems, Inc. Dr. Devgan will review the latest trends in artificial intelligence and machine learning and their impact on the EDA industry.
21 Posters will be presented on Tuesday, March 3 from 10:30am-noon.
Two panel sessions on Wednesday, March 4:

The panel, “New Chip Designs Create a Tidal Wave of Change” at 8:30am will be a Town Hall discussion on the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V. More information on the panel, including the list of panelists, can be found here.
The panel, “Predicting the Verification Flow of the Future” at 1:30pm will explore what the verification flow of the future will look like, attempting to predict the longevity of simulation and formal verification and determine how far emulation will be able to extend through the entire verification flow. More information on the panel, including a list of panelists, can be found here.

Three sponsored tutorials on Thursday, March 5:

“Next Generation Verification for the Era of AI/ML and 5G,” sponsored by Cadence Design Systems
“Application Optimized HW/SW Design & Verification of a Machine Learning SoC,” sponsored by Mentor, A Siemens Business
“Deploying VCS on Cloud for Faster Time to Market and Higher Quality Verification,” sponsored by Synopsys.

Attendees are encouraged to cast their votes throughout the conference for the Best Paper and Best Poster. The awards will be presented at the reception on Wednesday, March 4 at 4:45pm.

An essential part of DVCon is the opportunity to connect with colleagues in the industry. Attendees will have plenty of time to socialize and meet with peers and experts in the design and verification community throughout the conference as well as during the Expo, which will be held Monday from 5:00pm to 7:00pm and Tuesday and Wednesday from 2:30pm to 6:00pm.

For the complete DVCon U.S. 2020 schedule, including a list of tutorials, papers, short workshops, panels, posters, sponsored luncheons and events, visit https://dvcon.org/agenda. To view the videos from the DVCon U.S. 2019 Accellera Day tutorials, visit http://www.accellera.org/resources/videos/.

Visit https://dvcon.org/rates for more information on registration.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.