Highlights:
● Complete backside routing solutions enable next-generation high-performance chips for mobile, automotive, AI and hyperscale applications
● Cadence SF2 digital full flow includes advanced technology for nTSV optimization
● Backside implementation flow already proven with a successful SF2 test chip tapeout
SAN JOSE, Calif., June 28, 2023 —Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry’s SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence® digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. The flow has already been validated with the completion of a successful 2nm test chip tapeout.
The complete Cadence RTL-to-GDS flow that is optimized for the Samsung Foundry 2nm process technology includes the Genus™ Synthesis Solution, Innovus™ Implementation System, Integrity™ 3D-IC platform, Quantus™ Extraction Solution, Pegasus™ Verification System, Voltus™ IC Power Integrity Solution, Tempus™ Timing Signoff Solution and Tempus ECO Option. Backside routing improves PPA results and reduces congestion on the frontside layers and can be used for power distribution networks, clock tree nets and signal routing. Accordingly, the four Innovus Implementation System engines have been optimized for the Samsung Foundry 2nm process:
• Innovus GigaPlace engine automatically places and legalizes a nano through silicon via (nTSV) structure, allowing a connection between frontside and backside layers
• Innovus GigaOpt engine uses backside layers for timing-critical long wires to improve chip performance
• Innovus NanoRoute engine inherently supports backside routing based on rules in the technology’s Library Exchange Format (LEF)
In addition to the Innovus Implementation System engine capabilities that support SF2 technology, the Quantus Extraction Solution fully supports backside layers to enable the Tempus Timing Solution to sign off designs with a mix of frontside and backside layers, delivering reduced voltage drop on the power distribution mesh and improved routability on the frontside metal layers.
“Through our ongoing collaborations with Cadence, we’re consistently looking for new ways to help our mutual customers accelerate next-generation design innovation,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “The successful rollout of this backside design flow, fully supported by the Cadence digital flow, lets customers reap the benefits of our advanced SF2 technology.”
“Designers can speed time to market by leveraging our collaboration with Samsung Foundry on the complete RTL-to-GDS flow and SF2 technology,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “We’ve already seen a successful tapeout, and we’re looking forward to seeing our customers achieve many more design successes using our latest technologies.”
To learn more about Cadence’s advanced-node digital solutions, visit www.cadence.com/go/
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
