Accellera at DVCon U.S. 2023
Double Tree Hotel, San Jose, CA
Accellera Activities:
Monday, February 27, 2023
We hope you’ll join us for events focused on standards development! The following DVCon events are open to registered DVCon attendees (these events are not part of the free registration option). Registration is open >
9:00-Noon Tutorial: “User Experiences with the Portable Stimulus Standard”
The Accellera Portable Stimulus Standard is moving beyond the “bleeding edge.” As the Portable Stimulus Working Group continues to develop additional features of the language, many companies are adopting the standard in their verification flows. This technical tutorial will begin with an overview of the new features to be included in the coming update to the standard and will feature users from AMD and Intel who will share their experiences using this exciting new technology.
9:00-10:30 Workshop: “What is new in IP-XACT IEEE Std. 1685-2022?”
Accellera’s IP-XACT Working Group has been developing a proposal for a revision of IEEE Std. 1685-2014. The proposal was handed over to the IEEE P1685 Working Group in late 2021 and was approved by IEEE Standards Association Board in September of 2022. This workshop addresses the IP-XACT user community including IP and SoC companies, EDA vendors, and research institutes to inform them about upcoming changes in IEEE Std. 1685. It also addresses examples of commercial tool support for these changes.
11:00-12:30 Workshop: “Applications of the UVM-AMS Standard”
The Accellera UVM-AMS Standard will define an architecture and methodology to extend UVM testbenches from digital-only applications to DMS/real-number and AMS designs as well. This technical workshop will walk the audience through a worked example that will illustrate the key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments.
12:30-1:30 Accellera Luncheon: Featuring Bob Smith Executive Director, SEMI ESD Alliance
Join us for lunch and a captivating talk where Mr. Smith will present “The CHIPS Act and Its Impact on the Design & Verification Markets.”
3:30-5:00 Workshop: IEEE 1666-202X SystemC Sneak Peak
The next revision of IEEE 1666 SystemC is coming! It builds on enhancements and features contributed by the SystemC community during the last decade through the Accellera SystemC Language Working Group. This workshop will present some of the features of the upcoming revision, which modernize the language and enable new use cases. Target audience of this short workshop are system engineers, designers and architects who are familiar with SystemC simulation and modeling concepts and would like to know which new capabilities are being introduced to enable efficient Electronic System Level (ESL) design, systems modeling, or virtual prototyping in SystemC.
Wednesday, March 1, 2023
12:30-1:30 Accellera luncheon featuring Mark Himelstein, CTO RISC-V International
Join Accellera for a brief update on working group activities followed by a presentation by invited speaker Mark Himelstein, CTO of RISC-V, titled “RISC-V Everywhere.”
Thursday, March 2, 2023
12:30-1:30 Accellera Luncheon Featuring UVM 1800.2-2020-2.0 Library Discussion
UVM Working Group members will discuss the release of the 1800.2-2020-2.0 library. Presenters will focus on the implementation of the IEEE 1800.2-2020 standard to the library, with greatly enhanced backward-compatibility using code written for UVM1.1d or UVM1.2, creating some substantial performance improvements. Questions from attendees are welcome!
