SAN JOSE, CA – June 1, 2011 — ATopTech, the leader in next generation physical design solutions, will present significant technology additions and performance gains in its Aprisa™ and Apogee™ tools at DAC 2011 in San Diego. Aprisa is the company’s complete place and route (P&R) engine, including placement, clock tree synthesis, optimization, global routing, and detailed routing. Apogee is a complete top down floorplanning and chip assembly tool that complements Aprisa.
The latest release of Aprisa is 40% faster than previous versions, and Aprisa is now included in TSMC Reference Flow 12.0. TSMC and ATopTech collaborated in the development of Reference Flow 12.0 to address the increasing design challenges for 28nm and 40nm processes. Many new technologies–including 28nm design enablement, timing, reliability, low power and design for manufacturing (DFM) capability — have been implemented in Aprisa to enable customer design successes in smaller geometries.
“ATopTech continues to change the game in place and route,” said Jue-Hsien Chern, CEO of ATopTech. “The pace of innovation and development is unmatched in the industry.”
Highlights of the new innovations include:
“Time Warping” CTS
Aprisa has broken the boundary between optimization and Clock Tree Synthesis (CTS) that exists in conventional P&R tools. At DAC 2011, ATopTech is introducing the addition of “Time Warping” technology to Aprisa CTS. With “Time Warping CTS” technology, pre-route timing slack is improved with the concurrent efforts of the signal path optimization and the innovative skew group optimization, all while encompassing variability due to Multi-corner-multi-mode (MCMM) behavior.
Skew groups are automatically identified and their latency adjusted, either forward or backward in time, to efficiently reduce the total negative slack (TNS) of the design. This automatic and integrated capability substantially improves timing Quality of Results (QoR), especially for high performance designs, such as CPU or DSP cores.
Adaptive MCMM
Adaptive MCMM (Multi-corner-multi-mode) allows timing at multiple design corners and operational modes to be efficiently optimized during physical implementation. Aprisa’s MCMM optimization now includes three new complementary technologies, automatic and dynamic scenario selection, intelligent scenario grouping and concurrent scenario optimization, which, in combination, deliver more than 2X runtime and memory reduction for designs with increasing number of scenarios at 40nm/28nm. These new capabilities make it possible for all scenarios to be included during P&R optimization, dramatically improving the sign-off QoR and drastically reducing the Turn-around-Time (TAT) for the final timing closure.
In-Hierarchy Optimization (iHO)
In-Hierarchy Optimization (iHO) is Apogee¹s patent pending technology to enable fast top-level timing closure with simultaneous optimization at both top-level and blocks. The technology dramatically simplifies the top-level timing closure flow by avoiding timing re-budgeting and ECO between top-level and blocks, and hence reduces the timing closure effort from weeks to days. The proprietary Hierarchical Data Model of Aprisa/Apogee ensures extremely high capacity for advanced large designs.
iHO has been enhanced to support all stages of MCMM optimizations throughout the hierarchical flow to provide improved QoR and dramatically reduce the TAT of the designs. In one case, a customer was able to automatically close top-level timing on a 9M instance design in less than 24 hours when their original methodology took almost 30 days to do the job.
Stage-based On Chip Variation (SBOC)
Aprisa is the only tool available today to directly support SBOC optimizations within the place and route environment. In Aprisa, SBOC is supported in both timing updates and optimization, reducing the pessimism in standard on-chip variation (OCV) and yielding higher performance designs using fewer and smaller buffers.
Collaboration with Extreme DA on Aprisa/Goldtime correlation
ATopTech’s, physical design engine, Aprisa, is the leading solution for fast design closure that takes into account complex timing issues associated with SI and MCMM analysis. Extreme DA is licensing its timing analysis and sign-off technology to ATopTech for analysis correlation of leading edge digital integrated circuit (IC) designs. By combining the GoldTime timing analysis technology from Extreme DA, customers will have sign-off accurate insight to those paths that could affect circuit timing. This cooperation will result in meeting the performance challenges of verifying complex nanometer designs and deliver golden timing sign-off at 28nm and below.
About ATopTech
ATopTech, Inc., is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
