Ottawa, Canada – April 5, 2011 – Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, announced today that the Company’s SLP and ULP OTP product families have met the Assessment requirements of TSMC’s rigorous IP9000 program.
Sidense has many customers license their OTP macros at several process nodes and node variants, ranging from 180nm to 40nm. Completion of IP9000 Assessment of the 180nm SLP and ULP products represent only a small portion of the IP9000 evaluations Sidense products are currently undergoing; several more products at various process nodes are scheduled for the IP9000 Assessment evaluation later this year.
TSMC developed the rigorous IP9000 program to establish a set of requirements in order to assure the consistency, completeness and quality of IP provided by TSMC’s IP partners. It includes a multi-tiered process starting with the IP design and ultimately culminating in monitoring of yield during volume production to ensure the IP’s continued manufacturability. The IP9000 Assessment includes complete characterization of the IP over process, voltage, and temperature and full three-lot qualification. Passing this milestone demonstrates the IP’s readiness for volume manufacturing.
“Passing IP9000 acceptance criteria is recognized within the semiconductor IP industry as a demonstration of very high IP quality,” said Rhéal Gervais, Vice President of Operations at Sidense. “Meeting IP9000 Assessment gives our customers who use TSMC’s foundry services confidence that our 1T-Fuse™-based SLP and ULP OTP will meet their quality requirements.”
“We are pleased that these Sidense non-volatile memory IP products have passed TSMC’s IP9000 Assessment requirements,” said Dan Kochpatcharin, Deputy Director of IP Portfolio Marketing at TSMC. “During our IP9000 audit this past November, we found Sidense to be very well-prepared in terms of both QC and design methodology.”
About SLP and ULP
SLP is a smaller, lower power version of Sidense’s SiPROM product family with a maximum macro size of 256 Kbits. Initially manufactured at 180nm, SLP macros target cost- and power-sensitive applications such as handheld communication devices, chip and product IDs, analog trimming and calibration, and code storage. Sidense developed ULP as field-programmable eFuse replacements for precision analog trimming and calibration applications. Initially manufactured at 180nm, ULP macros are available from 16 bits to 2 Kbits and feature low power, low read voltage and fast start-up times.
About Sidense Corp.
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in over 150 customer designs, are available from 180nm down to 40nm and are scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com.
