industry news
Subscribe Now

Faraday Picks Silicon Frontline’s F3D for Accurate Post-Layout 3D Extraction of Analog and Digital Converters (ADCs)

Campbell, CA February 24,2011 – Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in the post-layout verification market focused on solutions for nanometer design applications, announced today that after an extensive evaluation of post-layout verification tool offerings Faraday picked Silicon Frontline’s F3D for its accurate 3D extraction. The high accuracy results of F3D for Faraday’s Analog to Digital Converters (ADCs) made it the only tool to match silicon and achieve the desired accuracy.

“Our highly sensitive ADC circuits have a very tight tolerance and we found that only Silicon Frontline’s F3D was capable of delivering the results we needed with exceptional performance and the required accuracy,” saidDr. Yu, Director of Faraday. “The matching of differential signals is critical in analog designs and F3D was able to highlight if and when any differences occurred.”

Silicon Frontline’s post-layout verification software delivers Guaranteed Accuracy, full-chip capacity and performance at least 20 times faster than other commercial field solvers. Users specify the level of accuracy desired, net by net, at the block level or with regular expressions. In this way, the resulting parasitics are guaranteed correct within the specified accuracy range for better design quality.

“Our 3D post-layout verification software continues to be accepted and used by the world’s leading semiconductor companies,” said Yuri Feinberg, CEO. “We are proud to have Faraday choose our highly accurate 3D post-layout extraction software product, F3D, for post-layout verification of its ADCs.

Silicon Frontline’s software has been used to accurately verify over 300 electronic designs to date. The company’s customers use its software to analyze power devices, improve image sensors, ADCs, flash memories, differential signals and nanometer and Analog Mixed Signal (A/MS) designs. The customer list includes 10 of the world’s top 30 semiconductor companies. In addition, leading foundries have validated Silicon Frontline’s products for use with their nanometer design technologies and reference flows.

About Silicon Frontline’s Products

F3D (Fast 3D) is used for fast 3D extraction and R3D (Resistive 3D) is used for 3D extraction and analysis of large resistive structures. F3D is chosen for its nanometer and Analog Mixed Signal (A/MS) design verification accuracy, and R3D for analysis that leads to improvements in the reliability and efficiency of semiconductor power devices.

About Silicon Frontline

Silicon Frontline Technology, Inc. provides post-layout verification software that is Guaranteed Accurate and works with existing design flows from major EDA vendors. Using new 3D technology, the company’s software products improve silicon quality for standard and advanced nanometer processes. For more information please visit www.siliconfrontline.com.For sales or general assistance, please email info@SiliconFrontline.com or sft@marubeni-sys.com.

Leave a Reply

featured blogs
Sep 11, 2024
In which we cogitate, ruminate, and pontificate on the things you can do to further your goal of landing (and keeping) a job in engineering...

featured paper

A game-changer for IP designers: design-stage verification

Sponsored by Siemens Digital Industries Software

In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, and learn how to run targeted, real-time or on-demand physical verification with precision, earlier in the layout process.

Read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
25,550 views