DUBLIN, IRELAND–(Marketwire – February 24, 2011) – Duolog Technologies, the award-winning developer of IP and SoC integration products, today announced that its Socrates Chip Integration Hub leverages a multi-standards-based methodology enabled through close collaboration with Cadence Design Systems, Inc. a leader in global electronic design innovation.
Duolog’s Socrates integration platform enables designers to manage metadata for their IP and systems through auto-generation of verification, hardware and software design data from a central, verified source to ensure that engineering teams remain synchronized at all times, and that costly bugs due to misalignment, miscommunication or misinterpretation are eradicated. Socrates employs industry standards including IP-XACT and UVM to support rapid SoC integration and a rich feature set for out-of-the-box interface automation for both hardware and software verification.
“Our award-winning Socrates platform employs vital standards, such as UVM and IP-XACT, and a strong Cadence collaboration to deliver the most comprehensive HW/SW integration solution in the industry, delivering against the EDA360 vision,” said David Murray, CTO, Duolog. “The starting point for this unique HW/SW integration solution is a validated machine-readable specification, from which we can derive multiple design views. Each view expresses the interfaces, code and functionality for a specific design task; one such view necessary for effective verification expresses the capabilities of the HW/SW interface. The requirements for this view have recently been ratified under the UVM standard as the UVM register package. Socrates produces this key UVM infrastructure automatically, and works with the Cadence Silicon Realization verification technologies.”
Socrates uses a unique “rules-based” IP assembly technology that eliminates the use of cumbersome and error-prone scripts. A few simple rules can generate thousands of lines of correct-by-construction interconnect in Verilog or VHDL. Equally important, concise rules files can be used to generate TLM / SystemC models for virtual prototypes or RTL models for FPGA prototypes in order to facilitate early software development, an important part of System Realization piece of the EDA360 vision.
“Effective system and SoC integration and verification continues to be elusive as product complexity increases,” said Michael Stellfox, distinguished engineer, System and SoC Realization Solutions Group at Cadence. “Rather than spending time debugging test bench infrastructure, verification engineers using Duolog’s solution can accelerate efficient HW/SW interface verification, a domain that is notorious for its bugs and inefficiencies. And, with a more predictable path for timely SoC integration verification, our mutual customers can shorten overall development time and cost. “
More information about realizing the EDA360 vision with Socrates is available at:http://www.duolog.com/socrates-realizing-eda360-vision
Socrates is a customer-extensible platform built on the superb Eclipse IDE and supporting the IP-XACT standard as well as many other open formats.
Duolog will be attending DVCon 2011 in San Jose, California, on March 1st and 2nd (booth #1105) where it will be demonstrating how the Socrates Hub improves SoC integration, verification efficiency and design team communications.
About Duolog Technologies
Duolog Technologies Ltd. is an award-winning developer of EDA tools that enable the flawless and rapid integration of today’s increasingly complex SoC, ASIC and FPGA designs. Duolog’s Socrates Chip Integration Hub employs a modular and extensible suite of tools for I/O layer definition, IP packaging, SoC connectivity, hierarchy manipulation and register management.
