SAN JOSE, Calif., Jan. 31, 2011 /PRNewswire/ — Xilinx, Inc. (Nasdaq: XLNX) today announced itsparticipation at DesignCon 2011 in Santa Clara, California from January 31 through February 3,2011. Throughout the week, Xilinx experts will share their insight about overcoming designchallenges, improving signal integrity problems, understanding Through Silicon Via (TSV) processes,and meeting chip to chip I/O demands. Xilinx will also be exhibiting demos with MoSys, SiSoft, andAgilent, all featuring Xilinx’s Virtex®-6 HXT FPGA. Xilinx Senior Vice President and Chief ofTechnology Officer, Ivo Bolsens, will keynote on how the industry is entering an era of crossover SoCs.
What: Xilinx at DesignCon 2011
Where: Santa Clara Convention Center (Santa Clara, Calif.)
When: Conference – January 31 – February 3, 2011Exhibits – February 1-2,2011
Keynote: Wednesday, February 212:00 – 12:30 pm, ChipHead Theater
Entering the Era of Crossover SoCs, Xilinx Sr. Vice President & CTO Ivo Bolsens
Global consumer markets continue to drive the need for ubiquitous computing and an insatiable thirstfor communications bandwidth, which are fueling the growth of the electronics industry. Yet the costof building custom SoCs to support many of the emerging applications is becoming increasinglydifficult to justify – except for the highest volume devices. Rising to this challenge, a new class of”crossover SoCs” is emerging that combines many of the strengths of custom SoCs and FPGAs in asingle device. In this session we will discuss the different approaches underway in the industry,including embedded processing subsystems, 3D interconnect technology, SiP and others, and howthey will reshape the device landscape over the next decade.
Panel Discussions:
Tuesday, February 13:45 – 5:00 pm, Ballroom F
FPGA Caveman meets FPGA Chiphead FPGA Design Tools and Methodologies: Can they keep pace?
Xilinx Sr. Vice President, Worldwide Marketing,Vin Ratford will join the panel in discussing theperformance and capabilities of 28nm FPGA devices and how FPGA vendors are providing ways forend users to integrate IP into FPGA architectures. This panel will examine the key pain points in theFPGA design process, look at unique design needs, and discuss new design tools, methodologiesas well as the greater opportunity for a true commercial FPGA EDA tool industry.
3:45 – 5:00 pm, Ballroom G
How to Avoid Butchering S Parameters
Xilinx Senior Staff Design Engineer, Mike Jenkins will join the panel in discussing ways to avoidproducing bad quality S parameter files for high speed serial channels. Specific topics will includecausality, passivity, reciprocity, de-embedding, reference planes, and measurement techniques.Through a discussion of the advantages and disadvantages of each point of view, attendees will gaina broader understanding of S parameters in general and what it takes to produce good S parameterfiles.
Wednesday, February 22:00 – 2:50 pm, ChipHead Theater
Back to Edison, Back to Innovation
Xilinx Sr. Vice President & CTO Ivo Bolsens will join an esteemed panel moderated by BDTI President Jeff Bier and including National Instruments President and CEO Dr. James Truchard andUniversity of California EECS Professor Edward Lee. Inspired by the June 5, 2010 issue of TIMEmagazine, which recounted the impact of Thomas Edison’s idea factory and his relevance today, thepanel will provide a modern look at Edison’s approach to ideas and results – “a minor invention every10 days and a big thing every six months or so” – taken from the January 3, 1888 page in Edison’sidea book.
3:30 – 4:30 pm, Room #208
Meeting chip to chip I/O demands of 100G & beyond line cards
Xilinx System Architect Communication Platform Definitions, Manoj Roge will join the panel indiscussing trends and alternative solutions for interconnecting chips on 100 Gbps & beyond linecards that maximize throughput while minimizing pin count, die area and power.3:45 – 5:00 pm, Ballroom GDesigning FPGA based PCBsXilinx Senior Director of Systems & Applications Engineering, Andy DeBaets will join the panel indiscussing the problems of designing FPGA based PCBs. This panel will address the designerchallenges of optimizing the FPGA design across multiple domains, schematics and FPGA timingand explore ways to solve them.Paper Session
Wednesday, February 29:20 – 10:00 am, Ballroom K
Through Silicon Via Design Considering Technology Challenges
Xilinx Staff Signal Integrity Engineer, Namhoon Kim will deliver a paper on a new approach forsuccessful implementation of TSV for multi-gigabit or tens-of-gigabit per second SerDes application,possible mechanical and reliability issues on TSV process, and will also cover technologyrequirements and common challenges.
Exhibition Demos
Tuesday-Wednesday, February 1-2
MoSys and Xilinx Virtex-6 HXT FPGA demo at Booth #516
As a new GigaChip Alliance participant, Xilinx will be showcasing a Virtex-6 HXT FPGA, theindustry’s highest bandwidth FPGA, interoperating with the MoSys Bandwidth Engine high densityserial memory at 10 Gbps. For more information on the GigaChip Alliance, please visit http://www.GigaChipAlliance.com.
SiSoft and Xilinx Virtex-6 HXT FPGA at Booth #100
Xilinx will be showing the hardware correlation of the Virtex-6 HXT FPGA GTH transceiver IBIS-AMImodel.
Agilent and Xilinx Virtex-6 HXT FPGA demo at Booth #201
Xilinx will be demonstrating the Virtex-6 HXT FPGA with the industry’s lowest-jitter 11Gbps+ serialtransceiver being analyzed by an Agilent DCA-X Digital Communications Analyzer.
For more information on Virtex-6 HXT FPGAs, please visit http://www.xilinx.com/products/virtex6/hxt.htm.
About DesignCon 2011
DesignCon is the essential design engineering event addressing the challenges facing thesemiconductor and electronic design engineer communities and providing the solutions attendeescan implement immediately in their designs. For more information, visit http://www.designcon.com.
About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com/.
