MOUNTAIN VIEW, Calif. – Jan. 27, 2011 – Jasper Design Automation today introduced ActiveProp(tm), an innovative new property synthesis tool that helps accelerate the adoption of assertion-based verification, including formal verification as well as simulation.
ActiveProp automatically generates high-level properties in industry-standard SystemVerilog Assertion (SVA) language, as well as human-readable reports, from RTL and simulation information. ActiveProp property synthesis helps expand the verification property set, increase functional coverage, and identify coverage holes, leading to higher-quality chip designs.
“ActiveProp delivers tremendous ROI by automating the creation of properties, producing high-quality results faster than ever thought possible,” said Kathryn Kranen, Jasper President and CEO. “Deploying ActiveProp standalone greatly improves verification efficiency for any assertion-based verification flow. It also has great synergy with Jasper formal solutions, to achieve faster proofs with JasperGold(R), and for design leverage with ActiveDesign(tm).”
ActiveProp generates intelligent, high-quality properties (assertions, constraints and covers) automatically, and multiple simulation runs can further refine the intelligence of generated properties. Unique multi-cycle analysis contributes to property quality, and generates properties where the causal effects are far removed from the resulting effects, not just two or three cycles away. ActiveProp also handles hierarchy, extracting properties across different modules and levels of hierarchy.
The inputs to ActiveProp are RTL, simulation information and scoped signals of interest which the user can control. Any simulation or testbench, block, system-level, or full SoC, can be used as input. ActiveProp simulator input can be provided in two ways, either running ActiveProp on previously created simulation files, or linked during run time with the simulator. ActiveProp outputs industry-standard SVA properties, which are used in any assertion-based design and verification flow.
ActiveProp also features a number of pre-defined checks including static checks; checks for common design errors such as arithmetic overflow, bus conflicts and illegal clock-domain crossings; coverage checks for errors such as dead-end and unreachable states; and more.
ActiveProp is currently available. For additional information contact Jasper, or visit www.jasper-da.com.
Learn More About ActiveProp At Upcoming Industry Events
ActiveProp will be featured at these upcoming industry events. To
register for a product demo, contact info@jasper-da.com.
- EDSFair, Jasper/CyberTec Booth #002, Yokohama, Japan, Jan. 27-28
- DesignCon Paper “Automating Higher Level Verification Methods via
- Property Synthesis,” Santa Clara, Calif., Feb. 3
- DVCon, Jasper Booth #704, San Jose, Calif., Feb. 28 – March 3
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 200 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.
