GiDEL Announces the Availability of TotalHistory™ a New Level in ASIC Prototyping and FPGA Debug

Kane Computing are pleased to announce that GiDEL has recently launched TotalHistory™, the most advanced debugging feature available in today’s ASIC Prototyping solutions and FPGA based systems.

TotalHistory is a software only solution enabling users to define a list of signals in the design which they want to trace at full system speed. There is practically no limit on the number of signals traced. The user can then view the trace using a waveform viewer to debug and validate the design. Optionally, an API is available for queries by advanced users.

“TotalHistory enables users to have visibility of any signal in their designs, for virtually unlimited trace depth, with no or minimal degradation in performance”, said Reuven Wientraub, GiDEL’s Founder and CTO. “TotalHistory opens the horizon for new debug and validation methodologies including dumping internal data while running at customer site, finding random glitches in long runs, etc. It leverages the unique architecture of our systems eliminating the need of additional costly hardware.”

TotalHistory is available with GiDEL’s PROC_SoC ASIC Prototyping Systems and PROC Boards FPGA-based High Performance Computing (HPC) accelerators.

About GiDEL

GiDEL (www.gidel.com) is the first company to introduce ASIC Prototyping Systems and FPGA-based Vision, imaging and HPC acceleration solutions. It consistently leads the market with cutting-edge architectures, solutions and methodologies.

About Kane Computing

KCL (www.kanecomputing.co.uk) has been providing Image Processing, DSP and high performance computing products for use in industry, education and research since 1987 and is a Texas Instruments Third Party Partner specialising in consultancy and advice on TI development tools/platforms and image processing applications. KCL have extensive knowledge and experience of providing video compression solutions for many industries particularly for digital video security and high quality broadcast applications. KCL has a policy of continual improvement and operates its business in accordance with the requirements of ISO9001:2000.

Cadence Silicon Realization End-to-End Verification Wins Design Tool and Development Software Category

SAN JOSE, Calif., and BRACKNELL, UK , 20 Dec 2010 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, is pleased to announce that the Cadence® Virtuoso® Accelerated Parallel Simulator has won the Elektra Electronics Industry Awards 2010 as the best design tool and development software. The Elektra Awards, established in 2003 and organized by Electronics Weekly and Reed Business Information in Europe, gives the industry an opportunity to recognize the achievements of individuals and companies across Europe.

“The entries in this category were very strong this year, but the judges felt the winner’s software tool could make a real impact on design cycles,” commented Richard Wilson, editor of Electronics Weekly and chairman of the judges.

The Virtuoso Accelerated Parallel Simulator (APS) addresses the challenges analog, mixed-signal, and RF designers face: accuracy degradation of results, excessive simulation run times and huge learning curve for setup and post processing. APS is part of the Virtuoso Multi-mode simulation platform – developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, for both pre- and post-layout designs.

“It is an honor to receive this award,” said David Desharnais, group director of product management at Cadence. “APS is a key element of Silicon Realization,which was outlined in the EDA360 vision. It enables our customers to boost productivity and provide unmatched performance for verification of very complex analog and mixed-signal IC designs.”

More information about Cadence Virtuoso Accelerated Simulator is available at the Cadence website.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Libby's Lab

Libby's Lab - Scopes Out Silicon Labs EFRxG22 Development Tools

Sponsored by Mouser Electronics and Silicon Labs

Join Libby in this episode of “Libby’s Lab” as she explores the Silicon Labs EFR32xG22 Development Tools, available at Mouser.com! These versatile tools are perfect for engineers developing wireless applications with Bluetooth®, Zigbee®, or proprietary protocols. Designed for energy efficiency and ease of use, the starter kit simplifies development for IoT, smart home, and industrial devices. From low-power IoT projects to fitness trackers and medical devices, these tools offer multi-protocol support, reliable performance, and hassle-free setup. Watch as Libby and Demo dive into how these tools can bring wireless projects to life. Keep your circuits charged and your ideas sparking!

Click here for more information about Silicon Labs xG22 Development Tools

featured chalk talk

Calibre DesignEnhancer: Layout Modifications that Improve your Design

Sponsored by Siemens Digital Industries Software

In this episode of Chalk Talk, Jeff Wilson from Siemens and Amelia Dalton investigate the variety of benefits that the Calibre DesignEnhancer brings to IC design and how this tool suite can be used to find and fix critical design stage issues. They also explore how the Calibre DesignEnhancer can Identify and resolve issues early in design flow with sign-off quality solutions and how you can utilize Calibre DesignEnhancer for your next design.

Click here to read the whitepaper called "Calibre DesignEnhancer design-stage layout modification improves power management faster and earlier"

Dec 16, 2024

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