Shanghai, China – November 15, 2010 – S2C Inc., a leading rapid SoC prototyping solutions provider,announced that S2C customers can now buy DDR2 and DDR3 Prototype Ready IP that work with S2C’s4th generation S4 TAI logic module. The Prototype Ready IPs enable customers to have out-of-box 2GBytes of DDR2 SDRAM operating at up to 533Mbps or 2GBytes of DDR3 SDRAM operating at up to800Mbps on S2C’s Altera Stratix IV based FPGA prototypes. Getting FPGA DDR2 and DDR3 memoriesto run at these high frequencies requires significant engineering. S2C has pre-engineered these designsto allow engineers to quickly create SoC prototypes.

The DDR2 and DDR3 Prototype Ready IPs utilize the memory controllers supplied by Altera QuartusSoftware and have been pre-mapped and fine tuned to work at high-performance with selected DDR2and DDR3 SO-DIMM memory tested by S2C. With the purchase, customer will get a TAI Player softwareproject file, which has the entire reference design already mapped to S4 TAI Logic Module, anddocumentation giving step by step instructions on how to run the DDR2 or DDR3 memory. Customer caneasily adjust DDR2/3 clock frequencies in the TAI Player software to verify that the read and writeoperations are correct at different clock speeds.

S2C’s DDR2 and DDR3 Prototype Ready IPs are useful reference designs to speed SoC development regardless of the actual memory controllers utilized in the final SoC implementation. S2C’s goal is toensure that customers can first get their SoC prototypes with DDR2 and DDR3 external memory up andrunning in shortest possible time with Altera’s supplied memory controllers. If customers have needs to verify their designs with the actual memory controllers in the SoC, the settings in the Prototype Ready IP such as pin assignments, timing constraints and other Altera Quartus settings can then be used as references.

“Large external SDRAM memory is often a critical element in today’s digital system design and there isan ever increasing need to have a stable SoC prototype on FPGA with large high-performance DDR2 andDDR3 external memories,” said Mon-Ren Chene, S2C’s Chairman and CTO. “Running DDR2 and DDR3at high-performance on FPGAs is not easy and if not engineered properly can lead to poor and unstable system performance. S2C’s DDR2 and DDR3 Prototype Ready Kits are pre-engineered to eliminatethese potential problems. Our goal is to continue to provide our customers with pre-engineered solutionsthat will shorten the time to achieve a working SoC prototype resulting in shortened design cycle enablingour customers to beat their competition to market.

“DDR2 and DDR3 Prototype Ready IPs are now available on all S4 TAI logic modules. The S4 TAI LogicModule is S2C’s 4th generation SoC prototyping hardware which facilitates much higher system prototype performance and reliability through enhanced power management, cooling mechanisms and noise shielding. S4 TAI Logic Module can mount either one or two Stratix IV FPGAs and supplies up to 30 million ASIC gates of capacity and provides 1,286 external I/O connections on one board. Multiple TAI Logic Modules can be stacked or mounted on a interconnect mother board to meet even larger gate count needs.

Rapid SoC Prototyping

S2C focus is on reducing SoC development times via rapid SoC prototyping. Our vision is to provide the SoC developer the tools and building blocks to rapidly create and verify the functionality of the SoC. Once the functionality is verified, the hardware and software development can begin in parallel. Using theSoC prototype as a software development platform is not only orders of magnitude faster than computes simulation but can surface errors sooner since the software is running in real system conditions. This hasa huge impact on SoC development schedules as software is increasing consuming SoC development resources. SoC development costs are soaring, but moreover the SoC Software development cost is thefastest rising cost. SoC Software is becoming the bottleneck for many projects as more functions aretightly integrated into a SoC and requires large number of engineers to develop and test software concurrently.