The swamp screams loudly around the abandoned road as the jousters position themselves for their impending bout. Somewhere, in the back of their alcohol-soaked brains, they visualize themselves as medieval warriors mounting their steeds in a duel of chivalrous wit. In the real world, their decrepit death-trap pickup trucks are a far cry from the mounts they mentally mimic, and the assembled audience of mosquitoes, flies, and the occasional bullfrog hardly constitutes the cheering throngs envisioned by these imbecilic soldiers of the sullen South.
With a final swig from their respective flasks of courage and a hearty “Yeee Haaa!!!” the two press their accelerators all the way to the floor, the lightly loaded rear tires fishtailing along the muddy road as the vehicles gain momentum. Each driver sees the headlights of the other’s vehicle growing rapidly brighter and farther apart through his windshield. Knuckles glow white on the steering wheels as both drivers and vehicles careen toward impending demise.
When egos and motivations (and sometimes a measure of testosterone) collide, some cultures call for resolution in what game theorists would term a “lose-lose scenario resulting from a negative-sum dispute.” You can tell from the terminology that game theorists seldom engage in activities such as “Chicken.” In this scenario, the participants are generally not mindful of the fact that participation in the conflict resolution process is likely to result in an outcome where everyone is worse off than when they started.
In the FPGA business culture, there is an unofficially scheduled biennial game of “Chicken” surrounding the announcement of new FPGA families based on smaller process geometries. The parameters of the game are as follows:
1) Nobody wants to announce a new family “too early.” Setting customer expectations that the new family will be available soon can be a bad thing, as it may forestall design-in decisions and/or result in unhappy customers. If my design team is about to start a project based on 65nm technology, but we think that by waiting a few weeks we might be able to design-in 45nm devices instead, we might just drag our feet a bit and work on the rest of our design while we wait for the newest, cheapest, fastest, lowest-power technology to be introduced. (Editor’s note: Never, ever do this.) If we then find out, however, that the new family won’t actually be shipping us chips for a year or two, we may not be such happy customers.
2) Everybody wants to announce before their competition. Just as my little brother used to think we were “winning” if there were no cars in view going our way in front of us, there is a perception in the marketing groups that being the “first” to announce a new family on the latest process node makes us engineers think that company is now the official technology leader.
These two factors are opposed to one another, as item 1 makes us want to delay announcement as long as possible and item 2 makes us want to announce as early as possible.
A third (and usually invisible) factor is that the announcement date is absolutely and completely arbitrary from a technical point of view. In truth, each FPGA vendor is simultaneously dealing with at least three or four process nodes at once. On the website, you’ll find the families that they are pushing us to design into our products right now. These are usually the latest-greatest devices on the smallest process nodes that are either shipping in volume or about to be shipping in volume (the case more often these days).
One would expect that these are the devices from which the bulk of the FPGA vendor revenue is derived, right?
Wrong.
Most of the revenue is from older devices that were designed into systems several years ago, and that are now being shipped in volume to fill those sockets. Xilinx and Altera both pump out far more 90nm and 130nm chips (yes and some 180nm ones as well) today than they do the “current” 65nm marketing warriors. Nonetheless, the sell for future business is to us as designers, and we’ll be using the newer generation devices for whatever we’re cooking up today.
While shipping us the older generations and selling us the current one, however, most FPGA companies also have at least two unannounced future process nodes under development at any given time. A crack team of semiconductor scientists is likely looking at how we’ll be making FPGAs in five or six years (two process nodes ahead), and a very active team of designers is engaged in the two-to-three year scope of the next unannounced process generation. Today, that means that FPGA companies are shipping 180, 130, 90, and some 65nm devices while working actively on both 45nm and 32nm architectures, processes, and products. This five-stage engineering pipeline has been pumping out technology for about two decades now, and it gets more refined with each passing process.
On the marketing side, then, we can really announce a new product family just about any time we want – given the fact that there really is no industry precedent for being able to ship products any time near announcement. With the current (65nm) FPGAs, the delay between “Here’s our new family” announcements and volume shipments of all the members of those families will weigh in at about two years. Interestingly enough, the time between process nodes is just about that same two years.
For Altera and Xilinx, for example, it has been right around two years since the first round of 65nm announcements. Both companies are now in (almost) full swing shipping products on that node. Xilinx got out with their high-end Virtex-5 well before Altera’s Stratix III, and Altera was pumping out tiny little low-cost Cyclone III devices at 65nm — and we’ve yet to hear about a 65nm sequel to Xilinx’s 90nm Spartan-3.
Can you hear the echo of the banjo? Is that the sound of a 1968 Ford F250 Camper Special with a run-out 360 V8 engine, a hole in the muffler, and a cracked head gasket revving somewhere in the backwaters of the swamp, with a Chevy 305 burning oil faster than gasoline chiming in singing whiskey tenor? Both FPGA vendors must be deciding when to announce their 45nm FPGAs right now, waiting as long as possible while still being “first”. At stake are marketing reputations, bragging rights in the more fashionable pubs in Silicon Valley, and the title of “PR-Chicken Champion” on the traveling trophy for the next two years… OK, maybe that’s an exaggeration, but – you get the idea.
We’d like to avert this madness, so we at FPGA Journal are going to step between these disaster-bound daredevils of determination. If we can de-fuse the situation just a little bit… OK, we’re letting the cat out of the bag. Both Xilinx and Altera will have 45nm FPGA families. There, we’ve said it. No need to worry about who will blink first. We get the upside of not having to search through tangled hulks of aging automotive metal to find our friends panting frantically “Did we beat them?”
Before you marketers start looking for the mole in your organizations, carrying out summary executions, strapping people into chairs and shining bright lights in their faces, we’ll just fess up – nobody told us. We’re simply reading the technological tea leaves as the parade of 45nm announcements starts long before the FPGA community comes out. If you hold up a timeline of each process node’s rollout for the last decade-plus, you’ll see for yourself that it’s almost time for the big media events, the 45nm parties, the speculative datasheets, the claims of comparative supremacy… We can hardly wait.
