Stacking the Die

FinFETs and the New Age of 3D ICs

by Amelia Dalton

It’s time for the FinFET rubber to meet the road. In this week’s Fish Fry, we look into the issues surrounding FinFET design today. My guest this week is Swami Venkat (Synopsys) and we chat about FinFET adoption (or lack thereof), the specific needs of FinFET design from an EDA point of view, and timing analysis in FinFET designs. Also this week, we check out how and why performance-per-watt will play an increasingly larger (and more important) role in our FinFET designs.

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Links for August 14, 2015

More information FinFET solutions from Synopsys

New Episode of Chalk Talk: Performance-per-Watt with FinFET-Based All Programmable Architectures

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

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featured chalk talk

MEG-Array and M Series

Sponsored by Mouser Electronics and Amphenol

In this episode of Chalk Talk, Jeremy Ellis from Amphenol Communications Solutions and Amelia Dalton chat about the benefits of Amphenol’s MEG-Array and M-Series connector solutions. They also investigate the tooling configurations available for these solutions and how Amphenol’s ball and socket BGA interface can simplify board routing, eliminate press-fit constraints on via and provide excellent SI performance.

Click here for more information about Amphenol FCI MEG-Array® Mezzanine Connector System

Oct 21, 2024

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Stacking the Die

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