Editors' Blog

Describing User-Defined Faults

In today’s article on cell-aware fault modeling, we described how specific layout-dependent faults can be accounted for in the test suite, increasing the test coverage beyond what stuck-at modeling provides and yet keeping the vector count down below what gate-exhaustive modeling would require.

But there has to be some way of defining these specific “user-defined” faults so that the test generation program can include them in the test suite.

Mentor devised their so-called “User-Defined Fault Model”, or UDFM, language … Read More → "Describing User-Defined Faults"

A Bit of Memory With Your Logic?

by Jim Turley

The recent ICCAD show had a session dedicated to MRAM and memristors. Spintec had a presentation on MRAM that went beyond the normal discussion of memory, and proposed a hybrid logic/memory (or logic-in-memory) usage of MRAM cells – or, more precisely, of magnetic tunnel junctions (MTJs).

At the very simplest end of this is a so-called non-volatile flip-flop (NVFF). It normally acts as a standard flip-flop or SRAM cell (with equivalent performance), but on the pull-up end of things are a couple … Read More → "A Bit of Memory With Your Logic?"

What Will the Next Logic Switch Look Like?

by Bryon Moyer

The recent edition of ICCAD provided an interesting look at what some of the contenders will be for logic switches once our standard configurations are no longer viable. Just to put things into perspective, FinFETs are old-tech in this timeframe.

One of the proposals stopped short of departing silicon: a silicon nano-wire FET. Imagine your standard Montana barbed-wire fence: three strands of wire between two posts. Now imagine that it snowed, and some kids piled up the snow like a wall running between the two fence posts so that the barbed wire strands were … Read More → "What Will the Next Logic Switch Look Like?"

Another Transistor Goes Vertical

by Amelia Dalton

While the recent MEMS Executive Congress focused on electro-mechanical applications, occasionally MEMS processing techniques were highlighted for strictly electrical purposes, with no mechanical component.

In one example, ICEMOS talked about their collaboration with MEMS manufacturer Omron for a new way of making superjunction power transistors.

Superjunction transistors overcome the R_on/breakdown tradeoff issue using alternating p and n stripes. In theory, these can be arranged a number of different ways, but, according to ICEMOS, the typical way it’s done now is horizontally, by growing a series of epitaxial layers of … Read More → "Another Transistor Goes Vertical"

A Different TSV

by Kevin Morris

Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.

But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t … Read More → "A Different TSV"

We Won’t Call You; Just Call Us

by Kevin Morris

One of the challenges with sensors is that, at their most fundamental level, all they do is provide some value reflecting whatever it is they’re sensing. If you want to know that value, you have to go get the value. “You” typically being the main processor in the system.

That’s easy enough if it’s something you occasionally do under the direction of a program, but if you want the sensor to alert you when something happens, then you have to poll constantly so that you know when something changed. … Read More → "We Won’t Call You; Just Call Us"

Getting a Jump on Power Integrity

by Kevin Morris

Apache announced their RTL Power Model (RPM) recently. The idea is that it lets designers understand their power and power integrity issues earlier in the design cycle. “Early,” however, is a relative term. Unlike some technologies that move such estimates to the architectural phase, this moves the capability from post-layout to RTL. That’s not to take anything away from it – they claim it gives designers a six-month jump on the problem.

The way this works involves a number of Apache tools, starting with PowerArtist. Actually, in order for PowerArtist to do its … Read More → "Getting a Jump on Power Integrity"

ESD on High-Frequency RF Circuits

by Jim Turley

In our recent piece on board-level ESD protection, I noted that, while the board is protected during actual usage, chip-level ESD protection is focused more on what might happen to the chip during handling, before it’s inserted into its final board resting place.

Such chip-level ESD circuits are mostly standard, typically involving some kind of diode breakdown to shunt excess energy. But this is apparently a dicier deal with RF circuits, since plain vanilla ESD circuits can degrade the RF performance.</ … Read More → "ESD on High-Frequency RF Circuits"

Virtual Platforms for a Non-FPGA

by Amelia Dalton

Xilinx has a new challenge on their hands. It’s called “software.” And at ARM TechCon, they announced their software enablement initiative for Zynq.

Of course, this is the same challenge any SoC project has. And SoC designers have a variety of tools to help with this, from virtual platforms to emulators. These allow software development to get up and running before the actual silicon is available.

What’s new is that Xilinx has their spiffy new Zynq family featuring the ARM Cortex A9 MPcore – one or more copies. And … Read More → "Virtual Platforms for a Non-FPGA"

Piezo… what?

by Amelia Dalton

The piezoelectric effect is pretty straightforward. With certain crystals, if you apply strain, the separation of dipoles in the crystal will set up a piezopotential.

Let’s take that one step further by making contacts on either end of a nanowire made of an appropriate material – in particular, ZnO, but potentially other so-called “wurtzite” semiconductors. Put a potential across is and use mechanical stress in the nanowire to modulate the current: you’ve basically got a FET, with the nanowire acting as a mechanical gate.

Those contacts are Schottky contacts, … Read More → "Piezo… what?"