Semiconductor
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Lattice Semiconductor’s Nexus 2 platform brings significant performance benefits to low-end FPGAs

While Altera and AMD continue to hammer away at the higher end of the FPGA spectrum – for example, see “AMD ups the ante in the RF-enabled FPGA poker game with the Versal RF family” – Lattice Semiconductor’s recent introduction of the Nexus 2 FPGA platform reconfirms the company’s commitment to smaller FPGA devices. Although the Nexus 2 platform employs … Read More → "Lattice Semiconductor’s Nexus 2 platform brings significant performance benefits to low-end FPGAs"

ST’s newest serial EEPROMs support both byte and page access

In 1973, the Miller Brewing Company launched the “lite” beer revolution with an ad campaign that proclaimed “Tastes great. Less filling.” The company’s ads backed up the slogan by showing very masculine athletes including Ray Nitschke, Ben Davidson, Bubba Smith, and John Madden drinking (or at least holding) glasses of the lite beer, to make it look more manly. Going back a bit earlier, the Peter Paul … Read More → "ST’s newest serial EEPROMs support both byte and page access"

AMD ups the ante in the RF-enabled FPGA poker game with the Versal RF family

AMD has made another play in the poker game for RF-capable FPGAs against Altera. AMD’s opening ante, actually Xilinx’s opening ante, was the introduction in early 2017 of the first RFSoC, based on the existing Zynq UltraScale+ SoC. Altera’s counter, in late 2022 back when Altera was still Intel, was to introduce the Agilex 9 Direct-RF series of FPGAs. The two companies have taken different manufacturing approaches … Read More → "AMD ups the ante in the RF-enabled FPGA poker game with the Versal RF family"

Ask Steve: Career and management advice from the former CEO of Microchip

It’s a new year and New Year’s resolutions may be on your mind. You’ll find some helpful hints on making resolutions, or just getting your career into gear, in Steve Sanghi’s new book, “Ask Steve: Everyday business advice from a successful CEO.” Sanghi based his new book on a decade’s worth of advice columns he wrote for the “Arizona Republic” newspaper from 2004 … Read More → "Ask Steve: Career and management advice from the former CEO of Microchip"

One More Step on the Path to AIIE (AI-In-Everything)

Almost anyone involved in developing new products today wants those products to have an artificial intelligence (AI) component [for the purposes of this column we will take AI to embrace machine learning (ML) and deep learning (DL)]. The problem is that AI is still very new in the scheme of things—everyone has heard about it, almost everybody uses it, but relatively few people know how to … Read More → "One More Step on the Path to AIIE (AI-In-Everything)"

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chalk talks
FPGA-based Prototyping with the Latest High-Capacity FPGA Enables New Use Modes – Siemens  FPGA-based prototyping is an essential tool for any SoC and digital chip design and verification. In this episode of Chalk Talk, Juergen Jaeger from Siemens and Amelia Dalton explore the multitude of benefits of the Veloce proFPGA CS platform from Siemens. They also investigate the debug capabilities, software prototyping and scalable hardware of this … Read More → "FPGA-based Prototyping with the Latest High-Capacity FPGA Enables New Use Modes – Siemens"
Calibre DesignEnhancer: Layout Modifications that Improve your Design – Siemens  In this episode of Chalk Talk, Jeff Wilson from Siemens and Amelia Dalton investigate the variety of benefits that the Calibre DesignEnhancer brings to IC design and how this tool suite can be used to find and fix critical design stage issues. They also explore how the Calibre DesignEnhancer can Identify and resolve issues … Read More → "Calibre DesignEnhancer: Layout Modifications that Improve your Design – Siemens"
Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff – Synopsys  The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology … Read More → "Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff – Synopsys"
Accelerating Tapeouts with Synopsys Cloud and AI — Synopsys  In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce … Read More → "Accelerating Tapeouts with Synopsys Cloud and AI — Synopsys"
SLM Silicon.da Introduction — Synopsys  In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform … Read More → "SLM Silicon.da Introduction — Synopsys"
Shift Left with Calibre — Siemens  In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens investigate the details of Calibre’s shift-left strategy. They take a closer look at how the tools and techniques in this design tool suite can help reduce signoff iterations and time to tapeout while also increasing design quality. Click here for more … Read More → "Shift Left with Calibre — Siemens"