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From Concept to Programmable Logic Prototype in Minutes

My poor old noggin is currently buzzing with ideas for things I could do with the new line of programmable devices that were recently introduced by the guys and gals at Texas Instruments.

As usual, of course, in addition to these new devices themselves, myriad ancillary thoughts are currently cavorting around my cranium.

Let’s start with Read More → "From Concept to Programmable Logic Prototype in Minutes"

From Thought to Circuit in Record Time with AI

Thus far, if the truth be told, I’ve had mixed experiences with large language models (LLMs) and generative artificial intelligence (GenAI) as personified by ChatGPT. I started, as many people do, by asking ChatGPT questions about things I knew nothing about, receiving responses that appeared to be reasonably impressive.

The reason for my emphasizing the word “appeared” in the previous … Read More → "From Thought to Circuit in Record Time with AI"

Eeek! GenAI-Powered Design and Verification EDA Tools

I just got off a video conference call with a company I cannot name that’s developed a technology I cannot discuss to power a product I am forbidden to talk about at this time. But I fear I’ve said too much. Suffice it to say that this product is going to enable a new generation of high-performance computing (HPC) and artificial intelligence (AI) platforms in … Read More → "Eeek! GenAI-Powered Design and Verification EDA Tools"

Want Automated, Certification-Level RISC-V Verification Coverage?

I feel like an old fool (but where are we going to find one at this time of the day?). Almost everything I hear on the technology front these days causes me to have a knee-jerk reaction along the lines of, “Things have certainly changed since those far-off days when I was a bright-eyed, bushy-tailed, newly-minted engineer!”

As I’ve mentioned before, I … Read More → "Want Automated, Certification-Level RISC-V Verification Coverage?"

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chalk talks
FPGA-based Prototyping with the Latest High-Capacity FPGA Enables New Use Modes – Siemens  FPGA-based prototyping is an essential tool for any SoC and digital chip design and verification. In this episode of Chalk Talk, Juergen Jaeger from Siemens and Amelia Dalton explore the multitude of benefits of the Veloce proFPGA CS platform from Siemens. They also investigate the debug capabilities, software prototyping and scalable hardware of this … Read More → "FPGA-based Prototyping with the Latest High-Capacity FPGA Enables New Use Modes – Siemens"
Calibre DesignEnhancer: Layout Modifications that Improve your Design – Siemens  In this episode of Chalk Talk, Jeff Wilson from Siemens and Amelia Dalton investigate the variety of benefits that the Calibre DesignEnhancer brings to IC design and how this tool suite can be used to find and fix critical design stage issues. They also explore how the Calibre DesignEnhancer can Identify and resolve issues … Read More → "Calibre DesignEnhancer: Layout Modifications that Improve your Design – Siemens"
Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff – Synopsys  The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology … Read More → "Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff – Synopsys"
Accelerating Tapeouts with Synopsys Cloud and AI — Synopsys  In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce … Read More → "Accelerating Tapeouts with Synopsys Cloud and AI — Synopsys"
Shift Left Block/Chip Design with Calibre — Siemens EDA   In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for … Read More → "Shift Left Block/Chip Design with Calibre — Siemens EDA"
SLM Silicon.da Introduction — Synopsys  In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform … Read More → "SLM Silicon.da Introduction — Synopsys"