It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for 3D IC DFT, naturally my interest was piqued. It’s an intriguing image, conjuring up thoughts of complex ways of managing tests on multiple dice.
Alas, as it turns out, there’s really no new technology associated with this: it’s simply the idea of allocating some TSVs for testing. Which is the same as allocating wires for test signals on a 2D chip.
So if the vertical ones are test elevators, then the plain-old wires we’ve been using should perhaps be called “test sidewalks” or “test freeways.”
At the end of the day, it’s just a metal connection.
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