There’s lots of interest in using germanium in pFETs to improve the symmetry between n- and p-channel devices in a CMOS inverter.  But integrating it with silicon has been challenging; at the very least, defects at the lattice interfaces have posed a significant barrier to progress.

Amongst the papers at IEDM, a couple featured ways of integrating Ge – literally – and confining defects.

A team from IBM, ST, Globalfoundries, Renesas, and Soitec devised a way of creating a uniform SiGe channel in a PMOS device on an extremely-thin SOI (ETSOI) wafer. This required moving to an isolation-last approach to avoid artifacts at the edges of the p-channel devices that would make performance layout-dependent. Instead, they blanketed the whole wafer with SiGe and selectively etched away the unneeded portions, leaving a layer of SiGe over the Si where the p-type channel was going to be. They then performed a “condensation” step – high-temperature oxidation that pushes the germanium from the SiGe layer into the silicon below it while oxidizing the silicon from the SiGe layer. Wide devices benefited from biaxial stress; narrow devices benefited even more from relaxation of perpendicular strain near the edges. In addition, back-gating can be used to modulate V_T for greater design flexibility. The only downside was leakage that was still acceptable, but higher than pure silicon.

The result was the fastest ring oscillator yet reported: 11.2 ps/stage at 0.7 V.

Meanwhile, TSMC was dealing with the defects created by simply attempting to grow germanium on silicon epitaxially. Ordinarily, this creates threads of dislocations that migrate up through the entire grown layer, making it unsuitable for active use. But they found that if they grow the germanium after isolation and if the feature being grown is taller than it is wide (aspect ratio > ~1.4), then those threads stop propagating up when they hit the sidewall. This leaves a fin with a damaged bottom, but with a pristine upper portion that can be used as a channel. They refer to this as Aspect Ratio Trapping (ART). They claim it’s the first successful integration of pure germanium onto a FinFET platform, yielding excellent subthreshold characteristics, high performance, and good control of short-channel effects.

If you have the proceedings, the ETSOI paper is #18.1; the TSMC paper is #23.5.