For decades the SoC design community has consistently lost ground in the battle to match advances in design technology productivity with the growth of available silicon technology. The silicon evolution roadmap has long been chronicled via Moore’s law, so how could the design community allow the existence of the well-known “Design Gap?” Understanding how we got to this point will make it easier to answer that question and make reasonable adjustments for the future, especially if there are obvious things to be learned from the evolution of many analogous industries.

Even in the … Read More → "Advancing FPGA Design Efficiency: A Proven Standard Solution"

His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success at each step. He will take three measured strides before his right foot strikes the ball slightly below center. He will follow through with his leg and keep his eyes riveted to the goal as the penalty kick tracks an arcing path through the air, catching the upper right corner of the net just out of the goalie’s reach. He exhales and begins the carefully choreographed sequence. As he nears … Read More → "Digital Do-Overs"

Introduction

High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.

Over the past decade, FPGAs have gained a foothold as one of the most used building blocks in digital systems. The flexibility of an FPGA allows designers to decrease hardware design cycles while adding inherent feature upgradability in the final product. In addition, the data rates of modern FPGAs are competing with CMOS ASICs, thus allowing the needed system performance to be achieved using … Read More → "FPGA I/O"

When was the last time you disassembled the package of each FPGA in your design to make sure the bonding is secure? Would your design criteria be different if shipping your device to its destination cost $13,000.00 per pound? What if your FPGA was in an environment where the radiation levels made random upsets of memory elements more the rule than the exception? If your device were operating in a vacuum, how would you think about heat dissipation? Would you work or think differently if an error in your design could result in loss of life, or in property damage … Read More → "FPGAs in Space"

Fifteen years ago verification of FPGA designs was easy: you only needed a decent gate-level simulator to verify a circuit containing several thousands of logic elements. As the size of FPGAs started to grow, so did the complexity of the designs implemented in them.

Over time, hardware description languages sneaked into schematic designs and eventually replaced schematic entry.

Today, it is quite common that FPGA users have to deal with more than one language in their designs (e.g. original sources in VHDL with some IP core in Verilog). At earlier stages of the design … Read More → "The Challenges of Modern FPGA Design Verification"

Why do we choose FPGAs? Usually because we want to get our design to market faster, cut our design cost and risk, and have more flexible, versatile products at the end. Because the process of customizing the FPGA is getting increasingly efficient, the development of a working board is rapidly becoming the long pole in the tent of our design process. Today, design teams are spending as much time getting the FPGA to work properly on the board and connected to the outside world as they are on any other major phase of the process.

Wouldn’ … Read More → "Mod Modules"

System platform-based design(1) is one of a number of high-level initiatives to tackle the spiraling problems of design complexity, hardware/software integrity and cost. The approach aims to stratify a system design problem into bite-size layers. It also aims to deliver higher, unified abstractions from existing digital EDA flows. Each platform must:

-map an instance in an (upper) application space to another in a (lower) architecture space
-communicate constraints between these spaces in forms suitable to each
-package the application solution in a form suitable for … Read More → "Programmable Analog for Platform-Based Design"

The contest begins. On the left side of the hall (the “blue” corner), the FPGA design team iterates through the design loop with their high-performance design tools, looking for the optimal placement to reach timing closure. As paths are probed and placements are optimized, it becomes apparent that the problem is the pin assignment. After swapping a few I/O constraints around and re-running place-and-route, the design clears timing analysis with flying colors. Positive slack for all!

On the right side of the hall (the “red” corner), this is all bad news. The … Read More → "Board Room"

Increased gate counts and higher clock speeds in programmable logic ICs have resulted in higher current requirements while smaller device geometries are driving lower core supply voltages. Simultaneously, new communications and memory technologies (DDR, DDR2) are requiring additional new supply voltages. Table 1 shows this low voltage trend in the generational progression of Xilinx FPGAs (Field Programmable Gate Arrays).

Table 1. Voltage Requirements of Xilinx FPGA Families