Imagine watching a professional sports contest (let’s say a basketball game), starting sometime in the middle. In this particular game, there is no visible scoreboard. You watch one team score, then the other. Each seems to be making progress and amassing points, but without a scorecard, you really have no way to tell who’s winning or losing.

There were two exciting announcements in the emerging low-cost, high-volume FPGA market this week. The key issue in this contest is, of course, price. Unfortunately, amidst the flurry of features, claims and specifications, price is the … Read More → "Low Cost Leapfrog"

I always believed that I was interested in electronics as a kid. I now see that I was wrong. After chatting with Ken McElvain at this year’s DAC, I learned that I was merely a poser, dabbling in the discovery of technology. Ken McElvain was interested in electronics. While I sat in my room with my Radio Shack 100-in-1 kit hooking up the multi-colored wires to the spring-loaded terminals, carefully constructing every pre-made project in the book, Ken McElvain was in the backyard with his dad, blowtorching TTL components off discarded circuit boards to stuff into wire-wrap … Read More → "Ken McElvain"

FPGAs are a great solution for prototyping because they offer designers the flexibility to test a design in the application without incurring large NRE charges. Design iterations can be performed using the same FPGA prototype device until the final working solution is attained. However, a completed design often requires a different set of priorities: lower cost, lower power and better performance. Structured ASICs offer a solution to this shift from a prototype emphasis to production design requirements at less risk than a comparable cell-based ASIC implementation. Structured ASICs also offer several key performance advantages over FPGAs, primarily in the … Read More → "Prototype to Production"

All the FPGA action these days is in the new, emerging markets right? As we’ve all discussed for awhile, CPLDs are a nice steady market with slow growth, and networking apps (the ones that built the FPGA industry to where it is today) took a nose-dive a few years back and are out of favor.

According to the world’s largest programmable logic company, this line of reasoning is a bit short-sighted. While Xilinx agrees that there are new and exciting emerging markets out there, they are pointing out, with two announcements this week, … Read More → "Xilinx Goes Retro"

It stands to reason.

Some components of system-on-chip design are static. You’re not going back and re-engineering them every two weeks. The multiplier was designed long ago and doesn’t really need to be designed again every time the moon changes phase. Neither does the PCI core, for that matter. They’re both stable and well-debugged. It’s unlikely that you’re ever going to need to modify or reconfigure them.

Why, then, does it make sense for these common functions to be built out of programmable logic, subject … Read More → "Semi-Programmable"

I  have now attended more than half of the 41 annual Design Automation Conferences. One of the things I’ve noticed during those twenty-odd years is that DAC started at the end of the design flow and moved forward. From the days when the hot topics in design automation were replacing tape and glass with Calma systems, the focus of DAC has been subjects closest to silicon. This, in turn, set the tone for the attendees as DAC’s content pushed its way from implementation details at the transistor level toward higher levels of design abstraction.

The 41st Design Automation Conference in San Diego last week wasn’t a bad conference. In fact, it was quite a good one. According to the program, there were a record number of papers submitted to the technical conference, and the selection panel had to be “more selective than ever” in choosing the elite few that were granted a session at DAC.

As a trade show, however, DAC is telegraphing ominous signals to the industry that supports it. Declining ASIC design starts, increasingly complex technical challenges, and rapidly improving alternative solutions threaten the very … Read More → "DAC’s Dangerous Undertones"

As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and unit-cost advantages of cell-based ASIC, unlikely alliances are inevitable. In this case, ASIC design tool leader Synopsys is teaming with leading FPGA vendor Altera to jointly develop solutions for the design and production of Structured ASICs.

Altera has long touted their HardCopy structured ASIC as a clean cost-reduction path from an FPGA-based development, prototype, and early production platform to a cost-reduced, performance-optimized mask-programmed equivalent. Altera is betting that the advantages of programmable … Read More → "Racing for the Gap"

In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we could successfully design correctly using current methodologies. Speculation ran rampant that large amounts of RAM, immense IP blocks, and system-on-chip integration would help us fill some of the space, but the overall question remained.

When FPGAs burst onto … Read More → "Virtex-4"

Introduction

Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a plug-in VME board with an Altera FPGA, embedded DiaLite virtual instrumentation from Temento Systems, and a TCL/TK-based custom human interface, an innovative solution was crafted that allows simple, multi-use analysis of the VME bus by engineers from different disciplines with widely varied levels of experience and expertise.

This article describes how DiaLite Instrumentation (DLI) was used to build a custom tool by taking advantage of the capability … Read More → "Leveraging On-Chip Debug for VME"