With the ever-increasing size and density of ASIC, conventional simulation-based verification has become a bottleneck in the project development cycle. In conventional verification, the simulation time steadily increases as the design matures in terms of bug count.

The verification community has resorted to different methodologies to overcome this. They are trying to reduce the development time by introducing Verification Components and Hardware Verification Languages (HVL). These help in terms of reusability but do not attend to the issue of simulation time. On one side, where the HVL provides better features such as higher … Read More → "Accelerating ASIC Verification with FPGA Verification Components"

It never makes the marketing materials. You don’t see an ad saying “New Super RISC Core is Stickier than Ever!” There is generally no mention of the word “sticky” in datasheets, white papers, or application notes. Suppliers of Intellectual Property (IP) cores (the overly-broad label that’s commonly applied to pre-engineered components that you can drop into your design, saving time, errors, and design effort) tout the speed, configurability, reliability, density, and power efficiency of their offerings, but never the “stickiness.” Unless you listen carefully to conversations in hallways, meeting … Read More → "Sticky Business"

The news has been slowly leaked like the plot to an upcoming summer blockbuster movie. First, there is “the teaser.” In movies, this is a 30 second preview that gives only the most basic hint of the film. In our case, this was Xilinx’s ASMBL architecture announcement that came out in December 2003. Xilinx outlined the next-generation floorplan, explaining that it would be rich in hard IP, grouped into what the company called “columns”. They also revealed that the new family would enable a number of product variants focused on different application domains. … Read More → "Virtex 4 Gets Real"

Unbelievable! FPGA Journal is running a feature article on a Xilinx organization change? What’s next, an exposé on Altera’s new carpets at corporate headquarters? Maybe an in-depth analysis of Lattice’s motivation for switching from Seattle’s Best to Stumptown coffee in their cafeteria? What happened to the concept of discriminating technical journalism?

While org-chart changes are certainly not our typical subject matter, we’re not just talking about a few ambitious executives forging a path up the corporate career ladder. We won’t repeat the details from … Read More → "What’s Your Persona?"

Professor Jason Cong’s office on the campus of UCLA is full, but not cluttered; important, but not pretentious; functional, but not over-designed. A wall of bookshelves that overlooks the desk and conference table is filled with proceedings from probably every technical conference ever to approach the subject of programmable logic design. One gets the impression that Professor Cong has not only read them all, but also participated in the production of a good percentage of them.

There is nothing in particular here to tip the casual visitor that this is the dojo where much of … Read More → "Jason Cong"

The first explorers came with Karnaugh maps and truth tables. Complex combinational functions could be concentrated in programmable logic devices more efficiently than with random logic parts or large, sparse ROMs. As these early PAL pioneers blazed trails into a new frontier of logic design, a culture of design methodology grew around them, and the process refined itself with design automation tools and techniques tailored to their needs.

Over time, programming PALs became less and less exclusive. The problems and pitfalls faced by early designers were known and solved, and automation techniques relegated programmable logic … Read More → "Methodology Melting Pot"

For decades the SoC design community has consistently lost ground in the battle to match advances in design technology productivity with the growth of available silicon technology. The silicon evolution roadmap has long been chronicled via Moore’s law, so how could the design community allow the existence of the well-known “Design Gap?” Understanding how we got to this point will make it easier to answer that question and make reasonable adjustments for the future, especially if there are obvious things to be learned from the evolution of many analogous industries.

Even in the … Read More → "Advancing FPGA Design Efficiency: A Proven Standard Solution"

His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success at each step. He will take three measured strides before his right foot strikes the ball slightly below center. He will follow through with his leg and keep his eyes riveted to the goal as the penalty kick tracks an arcing path through the air, catching the upper right corner of the net just out of the goalie’s reach. He exhales and begins the carefully choreographed sequence. As he nears … Read More → "Digital Do-Overs"

Introduction

High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.